Verilog-HDL Tutorial (1)

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    18-Jul-2015

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  • 1

    Verilog-HDL DE0(1) FPGA

    12, June, 2013

  • 2

    FPGA

    (Synthesis)

    ---- ---- ----

    Verilog-HDL

    module hoge( x, y, z); input x, y; output z; assign z = x & y; endmodule

    FPGA

  • 3

    Altera Quartus II

    *.v

    Verilog-HDL

    FPGA

    (Verilog-HDL)

    I/O

    *.v

    FPGA

  • 4

    Terasic DE0

    GPIO

    SDCard PS/2

    VGA USB

    AC

    7LED

    8MB SDRAM

    LED

    FPGA

  • 5

    FPGA

    EP3C16 F484 C6N

    FPGA: EP3C (Cyclone III) : 16 : F484 : 6

  • 6

    D2

    1 0 ()

    CD-ROM FPGA DE0 23