Verilog-HDL Tutorial (15) software

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Text of Verilog-HDL Tutorial (15) software

  • 1

    Verilog-HDL DE0(15-2) Nios II

    5, August, 2013

  • Nios II EDS (FPGA?)

    2

    Workspace () OK

  • BSP(Board Support Package)

    3

    BSP: Board Support Package ()

  • 4

    Hellow_NiosII_system.sopcinfo

  • 5

    (, NiosII/e)

    Hello_NiosII

    Hello World

    Next

  • 6 Finish

    Create a new BSP ...

  • 7

    hello_world.c

    2 ( )

  • 8

    Build Project

  • Build Console

    9

  • 10

    FPGA Nios II/e

    Run As Nios II Hardware

  • 11

    (FPGA) Nios II/e (PC) Nios II EDS

    Project name Project EFL le name

  • 12

    Target Connection

    System ID checks Ignore ()

  • 13

    Refresh Connections

  • 14

    Processors: Byte Stream Devices OK

    FPGAPC Apply Run

  • Nios II Console Hello from Nios II!OK

    15

    Downloading ELF Process failed , Quartus II Programmer . (JTAG USB ...)

  • system.h

    16

    GPIO32_OUT () IO (BASE Address) 0x1001090

  • io.h

    17

    IORD_32DIRECT: IO IORD_32DIRECT(, )

    IOWR_32DIRECT: IO IOWR_32DIRECT(, , )

  • hello_world.c

    18

  • Build ,

    19

    IORD_32DIRECT IOWR_32DIRECTLEDGIO

  • RS232CNios II/e

    20

    RS232C

  • 21

  • 22

    RS232C_test

    Hello World

    Next

    Hello_NiosII_system.sopcinfo

  • 23

    BSP ()

    Next

  • 24

    BSP RS232C

    Nios II BSP Editor ...

  • 25

    uart_0 (uart_0 Qsys UART Serial)

  • 26

    uart_0 jtag_uart_0 (JTAGNios II EDS System Console )

  • hello_world.c , Build -> Run

    27

  • RS232C

    28

    12, 13

    TEXT A TEXT

  • Console , LEDG

    29

    A: 0x41, 0100 0001

  • DE0 Qsys Nios II/e

    Nios II EDS

    , (),

    30

  • Qsys Nios II/e

    FPGA ()

    , Nios II EDS, LEDG () ON/OFF, LEDG RS232C, PCLEDG

    RS232C, PC

    (): io.h uart_0 "/dev/uart_0" . fopen, fprintf . , BSP .

    31