Verilog-HDL Tutorial (12)

Embed Size (px)

Text of Verilog-HDL Tutorial (12)

  1. 1. 1 Verilog-HDL DE0(12) RS232C(Rx) 31, July, 2013
  2. 2. UART 1 3: (GND), (TX), (RX) : 1 : , (, : Asynchronous Communication) (UART: Universal Asynchronous Receiver Transmitter) 2
  3. 3. RS232C 3 UART 3
  4. 4. DE0RS232C ()IC(ADM3202) 4
  5. 5. RS232C 5 5 4 3 2 1 9 8 7 6 1 2 3 4 5 6 7 8 9 RS232C .
  6. 6. RS232C (9600 bps) 6 (10) (8) LSB() (11) D0 D1 D2 D3 D7 9600 bps = 9600 bit per second , 1( ) 9600bit
  7. 7. RS232C 4 9600bps 4 7 (10) (8) LSB() (11) D0 D1 D2 D3 D7 30 D0 D1 D1
  8. 8. 50MHz 9600bps 4(, 38400Hz) 8 38400 Hz , 1= 1 / 38400 = 0.0000260416 [sec] 38400Hz , 0.0000260416 / 2 = 0.0000130208 [sec] High Low 50MHz50 MHz , 1= 1 / 50x106 = 0.02x10-6 [sec] , 0.0000130208 / (0.02 x 10-6) = 651.04 High Low (651)
  9. 9. PCLEDG 9 USB (BUFFALO) BSUSRC0605BS (amazon2011)
  10. 10. RS232C () 10 0000 0001 0010 0011 Reset LEDG