Verilog-HDL Tutorial (15) hardware

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  • 1

    Verilog-HDL DE0(15-1) NiosII

    5, August, 2013

  • Altera University Program Installer for Quartus II 13.0

    2

    http://www.altera.com/education/univ/software/upds/unv-upds.html Version 13.0 University Program Installer

  • 3

    ! (DE0TerasicCD-ROM )

    DE0CD-ROM Demonstrations "DE0_Top" C:verilogDE0_tutorial_15_Hello_NiosII

  • DE0_TOP.qpfQuartus II

    4

    Pin Planner

  • 5

    Quartus II Tools Qsys Qsys

  • Qsys Altera !

    6

    Avalon

    Nios II/e JTAG UART

    SDRAM Controller

    UART Serial Timer GPIO GPIO

    Clock (50MHz)

    Reset

  • University Program

    7

  • Avalon

    8

    Avalon

    Clock (50MHz)

    Reset

  • 9

    Embedded Processors

    Nios II Processor

    Add

  • 10

    Nios II/e Finish Nios II/e()

  • Nios II/e

    11

  • 12

    Avalon

    Nios II/e JTAG UART Clock (50MHz)

    Reset

  • 13

    Interface Protocols

    Serial

    Add

    JTAG UART

    FInish

  • 14

    Add

    UART RS232 Serial Port

    , FInish

    (bps)9600

  • 15

    Memories and Memory Controllers External Memory Interfaces

    16

    Add

    SDRAM Interfaces SDRAM Controller

    DE0

    , FInish

  • SDRAM

    16

    SDRAM Controller (new_sdram_controller) Rename

    sdram

  • 17

    Peripherals Debug and Performance

    Performance Counter Unit

    Add

    FInish

  • 18

    FInish

    Peripherals

    Microcontroller Peripherals Interval Timer

    Add

  • 19

    Microcontroller Peripherals PIO Parallel IO

    Add

    32

    Output

    , FInish

  • 20

    SDRAM , . GPIO32_OUT

  • 21

    Microcontroller Peripherals PIO Parallel IO

    Add

    32

    Input

    , FInish

  • 22

    GPIO32_IN Rename

  • 23

    University Program Clock Signals for DE-series Board Peripherals

    Add

    , FInish

    DE0

    Video

  • 24

    clocks Rename

  • 25

    , Avalon . . , DE0 (50MHz) University Program Clock (PLL) . .

  • 26

    clk.

  • 27

    . DE0 (BUTTON) JTAG UART (DE0 USBPC) , .

  • 28

    Nios II() .

  • 29

    Nios II() (instruction) SDRAM.

  • 30

    uart_0

    Quartus II Verilog-HDL, Verilog-HDL . , .

    UART RS232

  • 31

    SDRAM sdram_wire

    GPIO32_OUT gpio32_out ()

    GPIO32_IN gpio32_in

    Clock sdram_clk

  • ()

    32

    jtag_uart_0 5

    uart_0 8

    timer_0 6

  • Nios II/e IO

    33

  • 34

  • Nios II/e

    35

    nios2_qsys_0

    Reset Vector Reset vector memory sdram.s1

  • 36

    , Exception Vector sdram.s1

  • . .

    37 , MessagesErrorWarning (ErrorWarning, )

  • (Verilog-HDL)

    38

    Generation

    Generate

  • Qsys

    39

    Save

    Hello_NiosII_system

  • Generate Completed

    40

    Close

  • 41

    HDL Examples

    Copy

    Quartus II . , Qsys . , Quartus II . (Qsys)

  • 42

    Quartus II DE0_TOP.v ,

  • Qsys (.qsys)Quartus II

    43

    Project naviagtor DE0_TOP

    Settings ...

  • 44

    Category Files

    Qsys (Hello_NiosII_system.qsys)

  • 45

    Add All

    OK

  • 46

    OK

  • 47

  • Programmer FPGA

    48

  • Nios II EDS

    49