Examples Verilog HDL

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verilog

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    VERILOG HDL Examples

    1. DECODER

    //GATE LEVEL

    module decoder(d0,d1,d2,d3,x0,x1);

    input x1,x0;

    output d0,d1,d2,d3;

    wire w1,w2;

    not(w1,x1);

    not(w2,x0);

    and(d0,w1,w2);

    and(d1,w1,x0);

    and(d2,w2,x1);

    and(d3,x1,x0);

    endmodule

    //BEHAVIOURAL LEVEL

    module decb(d,e,x,y);

    output reg[3:0]d;

    input e,x,y;

    always @ (x or y or e)

    begin

    case ({x,y})

    2'b00: d=4'b0001;

    2'b01: d=4'b0010;

    2'b10: d=4'b0100;

    2'b11: d=4'b1000;

    endcase

    end

    endmodule

    //DATA FLOW

    module decd(d,x,y,e);

    input x,y,e;

    output [3:0]d;

    assign d[0]=((~x)&(~y)&e);

    assign d[1]=((~x)&(y)&e);

    assign d[2]=((x)&(~y)&e);

    assign d[3]=((x)&(y)&e);

    endmodule

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    2. DLATCH

    //GATE LEVEL

    module dlatgat(q,q1,d,e);

    input d,e;

    output q,q1;

    wire w1,w2,w3,w4;

    not (w2,d);

    not (w1,e);

    and (q,e,d);

    and (w3,w1,w2);

    xor (w4,e,d);

    or (q1,w3,w4);

    endmodule

    //BEHAVIORAL

    module dlatbeh(q,q1,d,e);

    input d;

    input reg e;

    output reg q,q1;

    always @e

    q = d;

    q1 = ~d;

    endmodule

    //DATAFLOW

    module dlatdata(q,q1,d,e);

    input d,e;

    output q,q1;

    wire w1,w2;

    assign w1=~(d&e);

    assign w2=~(w1&e);

    assign q=~(w1&q1);

    assign q1=~(w2&q);

    endmodule

    3. D FLIPFLOP

    //GATE LEVEL

    module dffgat(q,q1,d,e);

    input d,e;

    output q,q1;

    wire w1,w2,w3,w4;

    not (w2,d);

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    not (w1,e);

    and (q,e,d);

    and (w3,w1,w2);

    xor (w4,e,d);

    or (q1,w3,w4);

    endmodule

    //BEHAVIORAL

    module dff(q,q1,d,e);

    input d,en;

    output q,q1;

    always

    #5 en=~en;

    #50 $finish;

    always @posedge (en)

    q = d;

    q1 = ~d;

    endmodule

    //BEHAVIORAL

    module dff(q,q1,d,e);

    input d,en;

    output q,q1;

    always

    #5 en=~en;

    #50 $finish;

    always @posedge (en)

    q = d;

    q1 = ~d;

    endmodule

    4. MAGNITUDE COMPARATOR

    //GATELEVEL

    module magg(o1,o2,o3,a,b);

    input [1:0]a,b;

    output o1,o2,o3;

    wire [11:0] w;

    not (w[0],a[0]);

    not (w[1],a[1]);

    not (w[2],b[0]);

    not (w[3],b[1]);

    //a

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    and (w[5],b[0],w[1],w[0]);

    and (w[6],b[1],b[0],w[0]);

    or (o1,w[4],w[5],w[6]);

    //a=b

    xnor (w[7],a[1],b[1]);

    xnor (w[8],a[0],b[0]);

    and (o2,w[7],w[8]);

    //a>b

    and (w[9],w[3],a[1]);

    and (w[10],w[3],w[2],a[0]);

    and (w[11],a[1],a[0],w[2]);

    or (o3,w[9],w[10],w[11]);

    endmodule

    //BEHAVIORAL

    module magbeh(o1,o2,o3,a,b);

    input [1:0] a,b;

    output o1,o2,o3;

    always

    begin

    if(a>b) o1=1;o2=0;o3=0;

    else if(a == b) o1=0;o2=1;o3=0;

    else o1=0;o2=0;o3=1;

    end

    end

    endmodule

    //DATAFLOW

    module mag(o1,o2,o3,a,b);

    input [1:0] a,b;

    output o1,o2,o3;

    assign o1=(b[1]&~a[1])+(b[0]&~a[1]&~a[0])+(b[1]&b[0]&~a[0]);

    assign o2=(a[1]^~b[1])&(a[0]^~b[0]);

    assign o3=(a[1]&~b[1])+(a[0]&~b[1]&~b[0])+(a[1]&a[0]&~b[0]);

    endmodule

    5. Half Subtractor

    //GATELEVEL

    module HalfSub(i0, i1, bor, dif);

    input i0;

    input i1;

    output bor;

    output dif;

    wire i0n;

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    not(i0n,i0);

    xor(dif,i0,i1);

    and(bor,i0n,i1);

    endmodule

    6. Full Subtractor

    module FullSub(b_in, i1, i0, b_out, dif);

    input b_in;

    input i1;

    input i0;

    output b_out;

    output dif;

    assign {b_out,dif}=i0-i1-b_in;

    endmodule

    7. HALF ADDER

    //GATE LEVEL MODELLING

    module half(sum,carry,a,b);

    input a,b;

    output sum,carry;

    xor(sum,a,b);

    and(carry,a,b);

    endmodule

    //BEHAVIOURAL MODELLING

    module habehavioural(sum,carry,a,b);

    input a,b;

    output reg sum,carry;

    always@(a or b)

    begin

    if(a&b)

    begin

    sum=0;

    carry=1;

    end

    else if((a&~b)|(~a&~b))

    begin

    sum=1;

    carry=0;

    end

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    else if(~a&~b)

    begin

    sum=0;

    carry=0;

    end

    end

    endmodule

    //DATAFLOW MODELLING

    module hadataflow(sum,carry,a,b);

    input a,b;

    output sum,carry;

    assign {carry,sum}=a+b;

    endmodule

    8. FULL ADDER

    //GATE LEVEL MODELLING

    module fagate(sum,carry,a,b,c);

    input a,b,c;

    output sum,carry;

    wire w1,w2,w3;

    xor(sum,a,b,c);

    and(w1,a,b);

    and(w2,b,c);

    and(w3,a,c);

    or(carry,w1,w2,w3);

    endmodule

    //BEHAVIOURAL MODELLING

    module fabehavioural(sum,carry,a,b,c);

    input a,b,c;

    output reg sum,carry;

    always@(a or b or c)

    begin

    if(a&b&c)

    begin

    sum=1;

    carry=1;

    end

    else if((~a&b&c)|(a&b&c)|(a&b&~c))

    begin

    carry=1;

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    sum=0;

    end

    else if((~a&~b&~c)|(~a&b&~c)|(a&~b&~c))

    begin

    carry=0;

    sum=1;

    end

    else if(~a&~b&~c)

    begin

    carry=0;

    sum=0;

    end

    end

    endmodule

    //DATA FLOW MODELLING

    module fadata(sum,carry,a,b,c);

    input a,b,c;

    output sum,carry;

    assign {carry,sum}=a+b+c;

    endmodule

    9. EQUALITY DETECTOR

    //GATE LEVEL MODELLING

    module edgate(out,a0,a1,b0,b1);

    input a0,a1,b0,b1;

    output out;

    wire w1,w2;

    xnor(w1,a0,b0);

    xnor(w2,a1,b1);

    and(out,w1,w2);

    endmodule

    //BEHAVIOURAL MODELLING

    module edbehave(out,a0,a1,b0,b1);

    input a0,a1,b0,b1;

    output out;

    always

    begin

    if(a0==b0)

    if(a1==b1)

    out=1;

    else

    out=0;

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    else

    out=0;

    end

    end

    endmodule

    //DATAFLOW MODELLING

    module eddata(out,a0,b0,a1,b1);

    input a0,a1,b0,b1;

    output out;

    if(a0==b0)

    if(a1==b1)

    assign out=1;

    else

    assign out=0;

    else

    assign out=0;

    end

    endmodule

    10. Encoder

    module Encd2to4(i0, i1, i2, i3, out0, out1);

    input i0;

    input i1;

    input i2;

    input i3;

    output out0;

    output out1;

    reg out0,out1;

    always@(i0,i1,i2,i3)

    case({i0,i1,i2,i3})

    4'b1000:{out0,out1}=2'b00;

    4'b0100:{out0,out1}=2'b01;

    4'b0010:{out0,out1}=2'b10;

    4'b0001:{out0,out1}=2'b11;

    default: $display("Invalid");

    endcase

    endmodule

    11. COUNTER

    Synchronous Down Counter

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    module downcounter(q,clk);

    output [0:3]q;

    input clk;

    wire w2,w3,w4,w5,w6;

    not n1(w4,q[1]),

    n2(w5,q[2]),

    n3(w6,q[3]);

    and a1(w2,w5,w6),

    a2(w3,w2,w4);

    tff t0(q[3],1,clk),

    t1(q[2],w6,clk),

    t2(q[1],w2,clk),

    t3(q[0],w3,clk);

    endmodule

    //T Flip Flop

    module tff(q,qbar,t,clk);

    output q,qbar;

    input t,clk;

    reg q = 0;

    always @(posedge clk)

    if(t)

    q = ~q;

    else

    q = q;

    assign qbar = ~q;

    endmodule

    Synchronous up counter

    module upcounter(q,clk);

    output [0:3]q;

    input clk;

    wire w2,w3;

    and a1(w2,q[2],q[3]),

    a2(w3,w2,q[1]);

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    tff t0(q[3],1,clk),

    tff t1 (q[2],q[3],clk),

    tff t2 (q[1],w2,clk),

    tff t3 (q[0],w3,clk);

    endmodule

    //TFF:

    module tff(q,qbar,t,clk);

    output q,qbar;

    input t,clk;

    reg q = 0;

    always @(posedge clk)

    if(t)

    q = ~q;

    else

    q = q;

    assign qbar = ~q;

    endmodule

    Asynchronous down counter

    module asdowncounter(q,clk);

    output [3:0]q;

    input clk;

    tff t0(q[0],1,clk),

    t1(q[1],1,q[0]),

    t2(q[2],1,q[1]),

    t3(q[3],1,q[2]);

    endmodule

    //TFF:

    module tff(q,qbar,t,clk);

    output q,qbar;

    input t,clk;

    reg q = 0;

    always @(posedge clk)

    if(t)

    q = ~q;

    else

    q = q;

    assign qbar = ~q;

    endmodule

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    12. SHIFT REGISTER

    module reg11(s0,s1,ifin,rtin,clk,clr, pin, a);

    input s0,s1,ifin,rtin,clk,clr;

    input [3:0] pin;

    output [3:0] a;

    reg[3:0]a;

    always@(posedge clk or negedge clr)

    if (clr==0)

    a=4'b0000;

    else

    case({s1,s0})

    2'b00:a=a;

    2'b01:a={rtin,pin[3:1]};

    2'b10:a={pin[2:0],ifin};

    2'b11:a=pin;

    endcase

    endmodule

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