Design ExamplesDesign ExamplesDesign ExamplesDesign Examples

Gookyi Dennis A. N.Gookyi Dennis A. N.

SoC Design Lab.SoC Design Lab.

September.16.2014

ContentContent Bus Data Transfer General Purpose Input and Output Timers

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A Microcontroller System A Microcontroller System ArchitectureArchitecture The design example is going to be based on a

microcontroller system architecture below:

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Bus Bus A bus is a set of wires used to transport information

between two or more devices in a digital system Multiple devices are usually connected to a bus so a

technique known as multiplexing is used to avoid conflicts

In multiplexing, only one device can use the bus at a time

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Bus Structures: Tristate Bus Bus Structures: Tristate Bus Uses tristate buffers A typical tristate bus structure is shown below When module 1 wants to send a message “a” to

module 2:

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aa

1

a

1

Bus Structures: Tristate Bus Bus Structures: Tristate Bus An example of a tristate bus:

Suppose that an n-bit tristate buffer is connected onto a bus

When the enable control is asserted, the data is placed on the bus otherwise, the output of the buffer is in a high-impedance state

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enable

data[1:0] qout[1:0]

Bus Structures: Tristate Bus Bus Structures: Tristate Bus Code and testbench:

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Bus Structures: Tristate Bus Bus Structures: Tristate Bus RTL Schematic and Waveform:

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Bus Structures: Tristate Bus Bus Structures: Tristate Bus An example of a bidirectional bus:

A bidirectional bus is a connection of two tristate buffers in such a way that the input of one buffer is connected to the output of the other

The enable control of each buffer is used to control the data transfer direction

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send

data_to_bus[1:0]

receiveqout[1:0]

data_from_bus[1:0]

Bus Structures: Tristate Bus Bus Structures: Tristate Bus Code and testbench:

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Bus Structures: Tristate Bus Bus Structures: Tristate Bus RTL Schematic and Waveform:

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Bus Structures: Tristate Bus Bus Structures: Tristate Bus The problem with tristate bus structure is that each

transmit buffer needs to drive an amount of n(Cbout+Cin)

Cbout = capacitance of the tristate output bufferCbin = capacitance of the tristate input buffer

This amount of capacitive load is intolerant in some applications

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Bus Structures: Multiplexer-Bus Structures: Multiplexer-Based BusBased Bus

To avoid capacitive load, a multiplexer is used

The output signals Ti of n modules are routed to their destination through a multiplexer tree

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Bus Arbitration Bus Arbitration Since a bus is a shared resource, there must exist

some mechanism to the usage of the bus when multiple transmitters initiate a bus transfer

The operation that chooses one transmitter from multiple ones attempting to transmit data is called bus arbitration

The device used to perform the function of bus arbitration is know as a bus arbiter

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Daisy-Chain ArbitrationDaisy-Chain Arbitration When using daisy-chain arbitration, each module has

two inputs and two outputs as below:

Table showing inputs and outputs functions:

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Signal Port Description

Carry-in Input Indicates whether the preceding stage has been granted the bus or not

Request Input Used together with the carry-in to seek for the bus

Carry-out

Output Indicates whether the succeeding stage should be granted the bus or not

Grant Output Indicates that a particular stage has control of the bus

Gra

nt

Gra

nt

Gra

nt

Req

c_in

Req

Req

c_in

c_in

c_out

c_out

c_out

…Module 1 Module nModule 2

Daisy-Chain ArbitrationDaisy-Chain Arbitration A widely used implementation is shown below:

An example of a 4-request arbiter is shown below:

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Ci

Ri

Ci+1

Gi

G4

G3

G2

G1

R4

R3

R2

R1

C3

C2

C1

1

1

1

1

1

00

0

0

0

0

Daisy-Chain ArbitrationDaisy-Chain Arbitration Daisy-chain arbitration has the following issues:

The highest priority is always associated with the first module

Bus arbitration time is determined by the modules cascaded in the daisy chain

This may limit the system performance

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Radial Bus Arbitration Radial Bus Arbitration This make use of separate request and grant lines for

each module The request lines of all modules sharing the bus are

connected to a bus arbiter through which at most one grant line is asserted

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Req

Grant

Req

Req

Grant

Grant

Module 1

Module 2

Module n

Bus

Bus

arb

iter

Radial Bus Arbitration Radial Bus Arbitration A priority scheme known as round-robin priority is

used to overcome unfairness in most digital systems The device been served currently is made the lowest

priority while the device succeeding it is made the highest priority device

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Radial Bus Arbitration Radial Bus Arbitration The logic function of the next Pi is as follows next-Pi = anyg’.Pi + g(i-1)modn

Anyg = 0, no grant was issued, this causes the priority to remain unchanged

If a grant was issued, anyg = 1, which causes Pi+1 to be 1 in the next cycle

Circuit diagram for 4 requests

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Radial Bus Arbitration Radial Bus Arbitration Calculating the next priority when “g0” has been

asserted:

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1

0

0

0

1

0

0

0

0

0

0

0

1 1

0

0

0

0

0

0

1

Data TransferData Transfer The goal of buses is to transfer message from source

to destination Bus operates in units of cycles, messages and

transactionsA message is a logical unit of information transferred

between source and destinationTransaction consists of a sequence of messages that

are strongly related The types of data transfer include:

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Synchronous Data TransferSynchronous Data Transfer Each transfer is in synchronism with the clock signal The receiver samples and latches the data in a

specified edge of the clock Devices in synchronous bus system:

Synchronous bus transfers can be divided into:Single-clock bus cycleMultiple-clock bus cycle

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Device Use

Bus master

Generates address and command signals

Bus slave Receives and decodes address and command signals

Synchronous Data TransferSynchronous Data Transfer The single-cycle bus cycle only needs one clock cycle

to complete a data transfer as shown below: Read cycle

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At the posedge of the clock:•Bus master sends the address and command•Bus master latches data read on the previous cycle

At the negedge of the clock:•The bus slave sends the data

Synchronous Data TransferSynchronous Data Transfer The multiple-clock cycle requires multiple clock

cycles to complete a data transfer as shown below:

The actual clock cycles needed is determined by the operating speeds of the devices attached to the bus

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At the posedge of the first clock:•Bus master sends the address and command•Bus master latches data read on the previous cycle

At the negedge of the second clock:•The bus slave sends the data

Asynchronous Data TransferAsynchronous Data Transfer Here, data transfer mode occurs at random The data transfer cannot be predicted in advance The data transfer may be controlled by using:

Strobe schemeHandshaking scheme

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Asynchronous Data TransferAsynchronous Data Transfer In the strobe control scheme, only one control signal

called the strobe is needed When there is data to be transferred, the strobe

signal is enabled by either:The source device: source initiated transferThe destination device: destination initiated transfer

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Asynchronous Data TransferAsynchronous Data Transfer Source initiated transfer:

The data transfer from CPU to memory is an example of this king of transfer

The write control signal serves as the strobe signal

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The source device places data on the data bus and then asserts the strobe control signal to notify the destination device that the data is available

The destination device samples and stores onto its internal register at the negative edge of the strobe signal

Asynchronous Data TransferAsynchronous Data Transfer Destination initiated transfer:

Data transfer from memory location to CPU is an example

The read control signal serves as the strobe 29

Destination device asserts the strobe to request data from the source device Once the source receives the

strobe signal, it places the data on the data bus for a duration long enough for the destination device to read it

The destination device samples and stores the data and deasserts the strobe signal

Asynchronous Data TransferAsynchronous Data Transfer The strobe scheme assumes that the requested

device is always ready for data transfer once the strobe signal is asserted

This is not always the case because in a number of applications the requested device is not when requested to send data

This is a major disadvantage of the strobe scheme

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Asynchronous Data TransferAsynchronous Data Transfer Handshaking is a technique that allows a two-way

control scheme for asynchronous data transfer Each transfer is sequenced by the edges of two

signals:Request (req or valid)Acknowledge (ack)

In handshaking transfer, four events are performed:Ready (request)Data validData acceptance Acknowledge

Handshaking also take two forms:Source initiated transferDestination initiated transfer

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Asynchronous Data TransferAsynchronous Data Transfer Source initiated transfer:

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Ready:The destination device deasserts the ack and is ready to accept data

Data valid:The source device places data on the data bus and asserts the valid signal to notify the destination device that the data on the data bus is valid

Data acceptance:The destination device samples and latches the data and asserts the ack signal

Acknowledge:The source device invalidates data on the data bus and deasserts the valid signal

Asynchronous Data TransferAsynchronous Data Transfer Destination initiated transfer:

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Request:Destination device asserts the req signal to request data from the source device

Data valid:The source places data on the data bus and asserts the valid signal to notify the destination that the data is valid

Data acceptance:The destination device samples and latches the data and deassert the req signal

Acknowledge:Source invalidates the data and deasserts the valid signal

General-Purpose Input and General-Purpose Input and OutputOutput GPIO is a device that can be programmed into either

input, output or even bidirectional An example of a GPIO is a general-purpose parallel

port General-purpose parallel port is a device that can be

used as an input or output as required Features of general-purpose parallel port:

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Feature Description

8 bidirectional I/O pins

Data direction register (DDR) Determines which I/O pins are inputs and which are outputs

Port register (PORT) Holds the data written to the port

General-Purpose Input and General-Purpose Input and OutputOutput When using general purpose devices, two user’s

viewpoints of the device are taken into consideration:The hardware modelThe programming model

The two viewpoints are illustrated below:

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General-Purpose Input and General-Purpose Input and OutputOutput GPIO design example:

Here it is assumed that the direction of each port pin is separately controlled by an individual DDR bit

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DDR Bit Implication

0 Port_pin[i] set as input

1 Port_pin[i] set as output

General-Purpose Input and General-Purpose Input and OutputOutput Code for GPIO:

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General-Purpose Input and General-Purpose Input and OutputOutput RTL schematic:

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General-Purpose Input and General-Purpose Input and OutputOutput Waveform: load port

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Load port with value on the data_bus

General-Purpose Input and General-Purpose Input and OutputOutput Waveform: load DDR

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Load DDR with value on the data_busDDR bits indicates which ports on the port pin are input and which are outputs

DDR Bit Implication

0 Port_pin[i] set as input

1 Port_pin[i] set as output

General-Purpose Input and General-Purpose Input and OutputOutput Waveform: read port

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In reading port, the value on the port_pin becomes available on the data_bus

Timers Timers Timers are essential modules in microprocessor

systems Timers provide the following applications:

Event countingTime measurementPeriod measurementWaveform generationTime of day tracking Pulse-width measurement

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Basic Timer OperationsBasic Timer Operations The essential operations of timers and counters are

exactly the same A counter is called a timer if it is operated at a known

clock of fixed frequency Most timers are usually counters with programmable

operation modes The basic operation modes of timers include:

Terminal count (binary/BCD event counter)Rate generationMonostableSquare-wave generation

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Basic Timer OperationsBasic Timer Operations Block diagram of a typical timer is located below:

The latch register stores the initial value to be loaded into the timer

The timer register performs the actual counting operation

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Terminal CountTerminal Count A timer operating in a terminal count mode is shown

below:

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Terminal CountTerminal Count Code:

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Describe the latch register which is loaded from the databus controlled by the wr signalDescribes the timer register which is a binary count down counter with parallel load controlled by timer_load and enabled by timer_enable

Generates the out signal which signals the end of the counting process

Generates the timer_stop signal

Produces a one-cycle timer_load signal triggered by a wr input signal

Terminal CountTerminal Count RTL schematic:

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Terminal CountTerminal Count Testbench:

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Terminal CountTerminal Count Load data_bus and load latch in next posedge

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Terminal CountTerminal Count Load timer and start count down

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Terminal CountTerminal Count “out” is asserted when count gets to 0

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Monostable (One-Shot) Monostable (One-Shot) OperationOperation In this mode, the out terminal outputs a high-level

pulse for a duration equal to the number of clock pulses

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Monostable (One-Shot) Monostable (One-Shot) OperationOperation Code:

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Monostable (One-Shot) Monostable (One-Shot) OperationOperation Testbench:

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Monostable (One-Shot) Monostable (One-Shot) OperationOperation RTL schematic:

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Monostable (One-Shot) Monostable (One-Shot) OperationOperation Waveform:

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Load data_bus Load latch register

• Load timer register• Assert timer_enable

and out to start count down

Deassert timer_enable and out to indicate end of count