Verilog hdl design examples

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Verilog hdl design examples

Text of Verilog hdl design examples

  • 1. DDeessiiggnn EExxaammpplleessGGooookkyyii DDeennnniiss AA.. NN..SSooCC DDeessiiggnn LLaabb..September.16.2014

2. CCoonntteenntt Bus Data Transfer General Purpose Input and Output Timers2 3. A MMiiccrrooccoonnttrroolllleerr SSyysstteemmAArrcchhiitteeccttuurree The design example is going to be based on amicrocontroller system architecture below:3 4. BBuuss A bus is a set of wires used to transportinformation between two or more devices in adigital system Multiple devices are usually connected to a bus soa technique known as multiplexing is used to avoidconflicts In multiplexing, only one device can use the bus ata time4 5. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss Uses tristate buffers A typical tristate bus structure is shown below When module 1 wants to send a message a to module2:5a1aa1 6. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss An example of a tristate bus:Suppose that an n-bit tristate buffer is connectedonto a busWhen the enable control is asserted, the data isplaced on the bus otherwise, the output of the bufferis in a high-impedance state6enabledata[1:0] qout[1:0] 7. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss Code and testbench:7 8. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss RTL Schematic and Waveform:8 9. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss An example of a bidirectional bus:A bidirectional bus is a connection of two tristatebuffers in such a way that the input of one buffer isconnected to the output of the otherThe enable control of each buffer is used to controlthe data transfer direction9senddata_to_bus[1:0]receivedata_from_bus[1:0]qout[1:0] 10. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss Code and testbench:10 11. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss RTL Schematic and Waveform:11 12. Bus SSttrruuccttuurreess:: TTrriissttaattee BBuuss The problem with tristate bus structure is thateach transmit buffer needs to drive an amount ofn(Cbout+Cin)Cbout = capacitance of the tristate output bufferCbin = capacitance of the tristate input buffer This amount of capacitive load is intolerant insome applications12 13. Bus Structures: MMuullttiipplleexxeerr--BBaasseedd BBuuss To avoid capacitive load, a multiplexer is used The output signals Ti of n modules are routed totheir destination through a multiplexer tree13 14. BBuuss AArrbbiittrraattiioonn Since a bus is a shared resource, there must existsome mechanism to the usage of the bus whenmultiple transmitters initiate a bus transfer The operation that chooses one transmitter frommultiple ones attempting to transmit data is calledbus arbitration The device used to perform the function of busarbitration is know as a bus arbiter14 15. DDaaiissyy--CChhaaiinn AArrbbiittrraattiioonn When using daisy-chain arbitration, each module hastwo inputs and two outputs as below:Grant Table showing inputs and outputs functions:15Signal Port DescriptionCarry-in Input Indicates whether the preceding stage has been granted thebus or notRequest Input Used together with the carry-in to seek for the busCarry-out Output Indicates whether the succeeding stage should be granted thebus or notGrant Output Indicates that a particular stage has control of the busGrantGrantReqc_inReqc_in Reqc_inc_outc_outc_outModule 1 Module 2 Module n 16. DDaaiissyy--CChhaaiinn AArrbbiittrraattiioonn A widely used implementation is shown below: An example of a 4-request arbiter is shown below:16CiRiCi+1GiG1G2G3G4R1R2R3R4C3C1C2111110 00000 17. DDaaiissyy--CChhaaiinn AArrbbiittrraattiioonn Daisy-chain arbitration has the following issues:The highest priority is always associated with thefirst moduleBus arbitration time is determined by the modulescascaded in the daisy chain This may limit the system performance17 18. RRaaddiiaall BBuuss AArrbbiittrraattiioonn This make use of separate request and grant linesfor each module The request lines of all modules sharing the busare connected to a bus arbiter through which atmost one grant line is asserted18ReqGrantReqGrantReqGrantModule 1Module 2Module nBusBus arbiter 19. RRaaddiiaall BBuuss AArrbbiittrraattiioonn A priority scheme known as round-robin priority isused to overcome unfairness in most digital systems The device been served currently is made the lowestpriority while the device succeeding it is made thehighest priority device19 20. RRaaddiiaall BBuuss AArrbbiittrraattiioonn The logic function of the next Pi is as followsnext-Pi = anyg.Pi + g(i-1)modnAnyg = 0, no grant was issued, this causes thepriority to remain unchangedIf a grant was issued, anyg = 1, which causes Pi+1 tobe 1 in the next cycle Circuit diagram for 4 requests20 21. RRaaddiiaall BBuuss AArrbbiittrraattiioonn Calculating the next priority when g0 has beenasserted:21010010001 100000000001 22. DDaattaa TTrraannssffeerr The goal of buses is to transfer message fromsource to destination Bus operates in units of cycles, messages andtransactionsA message is a logical unit of informationtransferred between source and destinationTransaction consists of a sequence of messages thatare strongly related The types of data transfer include:22 23. SSyynncchhrroonnoouuss DDaattaa TTrraannssffeerr Each transfer is in synchronism with the clocksignal The receiver samples and latches the data in aspecified edge of the clock Devices in synchronous bus system: Synchronous bus transfers can be divided into:Single-clock bus cycleMultiple-clock bus cycle23Device UseBusmasterGenerates address and command signalsBus slave Receives and decodes address and command signals 24. SSyynncchhrroonnoouuss DDaattaa TTrraannssffeerr The single-cycle bus cycle only needs one clockcycle to complete a data transfer as shown below: Read cycle24At the posedge of the clock:Bus master sends the address andcommandBus master latches data read on theprevious cycleAt the negedge of the clock:The bus slave sends the data 25. SSyynncchhrroonnoouuss DDaattaa TTrraannssffeerr The multiple-clock cycle requires multiple clockcycles to complete a data transfer as shown below: The actual clock cycles needed is determined by theoperating speeds of the devices attached to the bus25At the posedge of the first clock:Bus master sends the address andcommandBus master latches data read on theprevious cycleAt the negedge of the second clock:The bus slave sends the data 26. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr Here, data transfer mode occurs at random The data transfer cannot be predicted in advance The data transfer may be controlled by using:Strobe schemeHandshaking scheme26 27. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr In the strobe control scheme, only one controlsignal called the strobe is needed When there is data to be transferred, the strobesignal is enabled by either:The source device: source initiated transferThe destination device: destination initiatedtransfer27 28. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr Source initiated transfer: The data transfer from CPU to memory is an exampleof this king of transferThe write control signal serves as the strobe signal28The source device places data on thedata bus and then asserts the strobecontrol signal to notify the destinationdevice that the data is availableThe destination device samples and storesonto its internal register at the negativeedge of the strobe signal 29. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr Destination initiated transfer:Destination device asserts thestrobe to request data from thesource device Once the source receives the strobesignal, it places the data on the databus for a duration long enough forthe destination device to read itThe destination devicesamples and stores the dataand deasserts the strobesignal Data transfer from memory location to CPU is anexampleThe read control signal serves as the strobe 29 30. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr The strobe scheme assumes that the requested deviceis always ready for data transfer once the strobesignal is asserted This is not always the case because in a number ofapplications the requested device is not whenrequested to send data This is a major disadvantage of the strobe scheme30 31. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr Handshaking is a technique that allows a two-waycontrol scheme for asynchronous data transfer Each transfer is sequenced by the edges of twosignals:Request (req or valid)Acknowledge (ack) In handshaking transfer, four events are performed:Ready (request)Data validData acceptanceAcknowledge Handshaking also take two forms:Source initiated transferDestination initiated transfer31 32. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr Source initiated transfer:32Ready:The destination devicedeasserts the ack and isready to accept data Data valid:Data acceptance:The destination device samples andlatches the data and asserts the acksignalThe source device places data on thedata bus and asserts the valid signal tonotify the destination device that the dataon the data bus is validAcknowledge:The source device invalidates dataon the data bus and deasserts thevalid signal 33. AAssyynncchhrroonnoouuss DDaattaa TTrraannssffeerr Destination initiated transfer:33Request:Destination device asserts the req signalto request data from the source deviceData acceptance:The destination device samplesand latches the data anddeassert the req signalAcknowledge:Source invalidates the dataand deasserts the valid signalData valid:The source places data on the data busand asserts the valid signal to notify thedestination that the data is valid 34. General-PPuurrppoossee IInnppuutt aanndd OOuuttppuutt GPIO is a device that can be programmed into eitherinput, output or even bidirectional An example of a GPIO is a general-purpose parallelport General-purpose parallel port is a device that canbe used as an input or output as required Features of general-purpose parallel port:34Feature Description8 bidirectional I/O pinsData direction register (D