Verilog HDL Reference Manual

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FPGA Compiler II / FPGA Express Verilog HDL Reference ManualVersion 1999.05, May 1999

Comments? E-mail your comments about Synopsys documentation to doc@synopsys.com

Copyright Notice and Proprietary Information

Copyright 1999 Synopsys, Inc. All rights reserved. This software and documentation are owned by Synopsys, Inc., and furnished under a license agreement. The software and documentation may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

Right to Copy DocumentationThe license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.

Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the readers responsibility to determine the applicable regulations and to comply with them.

DisclaimerSYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

Registered TrademarksSynopsys, the Synopsys logo, BiNMOS-CBA, CMOS-CBA, COSSAP DESIGN (ARROWS), DesignPower, DesignWare, , dont_use, Eagle Design Automation, ExpressModel, in-Sync, LM-1000, LM-1200, Logic Modeling, Logic Modeling (logo), Memory Architect, ModelAccess, ModelTools, PathMill, PLdebug, Powerview, Retargeter, SmartLicense, SmartLogic, SmartModel, SmartModels, SNUG, SOLV-IT!, SourceModel Library, Stream Driven Simulator_, Synopsys, Synopsys (logo), Synopsys VHDL Compiler, Synthetic Designs, Synthetic Libraries, TestBench Manager, TimeMill, ViewBase, ViewData, ViewDoc, ViewDraw, ViewFault, ViewFlow, VIEWFPGA, ViewGen, Viewlogic, ViewPlace, ViewPLD, ViewScript, ViewSim, ViewState, ViewSynthesis, ViewText, Workview, Workview Office, and Workview Plus are registered trademarks of Synopsys, Inc.

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FPGA Compiler II / FPGA Express Verilog HDL Reference Manual, Version 1999.05

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About This ManualThis manual describes the Verilog portion of Synopsys FPGA Compiler II / FPGA Express application, part of the Synopsys suite of synthesis tools. FPGA Compiler II / FPGA Express reads an RTL Verilog HDL model of a discrete electronic system and synthesizes this description into a gate-level netlist. FPGA Compiler II / FPGA Express supports v1.6 of the Verilog language. Deviations from the definition of the Verilog language are explicitly noted. Constructs added in versions subsequent to Verilog 1.6 might not be supported. Aspects of the Verilog language that are not supported are listed in Appendix B.

AudienceThis manual is written for logic designers and electronic engineers who are familiar with Synopsys synthesis products. Knowledge of the Verilog language is required, and knowledge of a high-level programming language is helpful.

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Other Sources of InformationThe resources in the following sections provide additional information: Related Publications SolvNET Online Help Customer Support

Related PublicationsThese Synopsys documents supply additional information:

FPGA Compiler II / FPGA Express Getting Started Manual Design Compiler Command-Line Interface Guide Design Compiler Reference Manual: Constraints and Timing Design Compiler Reference Manual: Optimization and Timing Analysis Design Compiler Tutorial Design Compiler User Guide DesignWare Developer Guide VSS User Guide

Man PagesYou can view man pages from fc2_shell / fe_shell environment. From the shell prompt, enter:

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fc2_shell> help command_name

orfe_shell> help command_name

SolvNET Online HelpSOLV-IT! is the Synopsys electronic knowledge base. It contains information about Synopsys and its tools and is updated daily. Access SOLV-IT! through e-mail or through the World Wide Web (WWW). For more information about SOLV-IT!, send e-mail tosolvitfb@synopsys.com

or view the Synopsys Web page athttp://www.synopsys.com

Customer SupportIf you have problems, questions, or suggestions, contact the Synopsys Technical Support Center in one of the following ways: Send e-mail tosupport_center@synopsys.com

Call (650) 584-4200 outside the continental United States or call (800) 245-8005 inside the continental United States, from 7 a.m. to 5:30 p.m. Pacific time, Monday through Friday. Send a fax to (650) 584-2539.

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ConventionsThe following conventions are used in Synopsys documentation.Convention courier Description Indicates command syntax. In command syntax and examples, shows system prompts, text from files, error messages, and reports printed by the system. Indicates a user specification, such as object_name In command syntax and examples, indicates user input (text the user types verbatim). Denotes optional parameters, such as pin1 [pin2, . . pinN] Indicates a choice among alternatives, such as low | medium | high This example indicates that you can enter one of three possible values for an option: low, medium, or high. Connects two terms that are read as a single term by the system. For example, design_space. Indicates a keyboard combination, such as holding down the Ctrl key and pressing c. Indicates a continuation of a command line. Indicates levels of directory structure. Shows a menu selection. Edit is the menu name and Copy is the item on the menu.

courier italiccourier bold [ ] |

_

(Ctrl-c) \ / Edit > Copy

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Table of ContentsAbout This Manual 1. FPGA Compiler II / FPGA Express with Verilog HDL Hardware Description Languages . . . . . . . . . . . . . . . . . . . . . . . . . . FPGA Compiler II / FPGA Express and the Design Process . . . . . 1-2 1-4

Using FPGA Compiler II / FPGA Express to Compile a Verilog HDL Design 1-5 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Description Styles Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structural Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixing Structural and Functional Descriptions . . . . . . . . . . . . . . . . Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Language Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-3 2-4 2-6 2-6 2-6 1-6

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Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Structural Descriptions Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macromodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Definitions . . . . .