Verilog HDL Lab Manual

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Verilog HDL Lab Manual

Dated: 29/04/2011

FPGA DESIGN FLOW8.1 Programmable Logic Design FlowDesign Specifications Design Entry Functional Simulation (Zero Delay)

RTL Model Target Device Libraries (Vender Specific) Design Constraints Area / Speed

T E S T B E N C H

Gate level Simulation

Synthesis Gate level description using target library cells

Gate level Model Timing Simulation (Gate + Interconnect Delays) Mapping + Translation Gate level model to device architecture Place and Route Placing the design in device while optimizing it for speed and area Programming file generation Bit Stream Download onto FPGA/ CPLD

Target Device Libraries (Vender Specific) Design Constraints Area / Speed

Libraries (Simprims and Unisims)

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

Verilog HDL Lab Manual

Dated: 29/04/2011

FPGA Design Flow for XilinxThe Design flow followed by Xilinx devices is as shown as under:

Xilinx FPGAs are reprogrammable and when combined with an HDL design flow can greatly reduce the design and verification cycle.

Broadly the stages can be categorized as: Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

1.

2. 3. 4.

Verilog HDL Lab Manual Dated: 29/04/2011 Design Entry may have two alternatives: a) Performing HDL coding for synthesis as the target.( Xilinx HDL Editor). b) Using Cores(Xilinx Core Generator). Functional Simulation of synthesizable HDL code (MTI ModelSim). Design Synthesis ( Xilinx project navigator). Design Implementation (Xilinx Design Manager).

The stages are linked as follows:

VERILOG HDL/Verilog Code Design Entry Functional Simulation

Synthesis

Post Synthesis Simulation

Implementation

Timing Simulation

Program onto FPGA

Design EntryThe first stage of Xilinx design flow is a design entry process. A design must be specified by using either a schematic editor or HDL text-based tool.

Functional SimulationUpon the finish of the design entry stage, the functional simulation of the design is being performed, which is used to verify functionality of the design assuming no delays, whatsoever. This assumes no target technology selection at this stage and hence assumes zero delay in simulation. Complex designs must be intensively simulated, at different simulation points, during the design flow. Simulation verifies the operation of the design before it is actually implemented as hardware. One of the most prevalent methods for simulation is testbenching. Testbenches (VERILOG HDL) or text fixtures (Verilog) are used to specify circuit stimuli and responses. Roughly, simulation can be divided as functional and timing simulation. Primarily, the functional simulation verifies that the designs specifications are correctly understood and coded. Timing information, produced Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

Verilog HDL Lab Manual Dated: 29/04/2011 during the device implementation stage, is not available during the functional simulation. Functional simulation can be used after synthesis, too. Comparison between the pre- and post-synthesis simulations results checks the results of the HDL compilers work and the HDL codes correctness. Timing simulation operates with the real delays (results of device implementation) and is used for verification of implemented design. Timing data are given in an .sdf file (Standard Delay Format). Xilinx supports functional and timing simulations at different points of the design flow: Register Transfer Level (RTL) simulation. Post-synthesis functional simulation (Pre-NGDBuild). Post-implementation back-annotated timing simulation.

Design SynthesisAfter this process, the synthesis is performed. Here for the first time in the design flow the target technology (choice of a particular FPGA device family) is being performed. This target technology selection will remain the same, henceforth in the design flow, upto the final implementation stage, where finally generated Bit stream file gets downloaded onto that FPGA. The output of the synthesis process is creation of gate level netlist. This refers to the EDIF implementation netlist of the FPGA design. Besides the EDIF implementation netlist, the XNF (Xilinx netlist format) netlist can be used as well. Although the XNF is now becoming rather obsolete. The EDIF netlist is used as an input file to the Xilinx Implementation tool and specifies how the core will be implemented. The Electronic Design Interchange Format (EDIF) is a format used to exchange design data between different CAD systems. In the world of FPGA design, it is used for interchange of data between different EDA (Electronic Design Automation) software tools. EDIF files are used for FPGA implementation only. They are the result of design synthesis and can be generated from different design entry EDA tools: schematic or HDL design tools. EDIF files are inputs to the Xilinx implementation tools during the translation step (NGDBuild).

Design ImplementationDesign Implementation includes the following steps: i) Translate ii) Map iii) Place and Route In the Translate step, which is the first step in the implementation process, EDIF netlist must be further converted into Native Generic Database file (NGD), by means of a program called NGDBuild. The NGD file resulting from an NGDBuild run contains the logical description of the design that can be mapped into a targeted Xilinx FPGA device family. It is important to stress that NGDBuild merges all available EDIF netlists from the working directory. This is actually the step where the black-box netlist becomes merged with the rest of FPGA design. In the next stage, the Map stage, the NGD file is an input into a MAP program that maps logical design to a Xilinx FPGA. The output of the MAP program is an NCD (Native Circuit Description) file. The NCD is a physical representation of the design mapped to the components of internal FPGA architecture. The mapped design is ready to be placed and routed. The PAR program does this job. The input to PAR is a mapped (not routed) NCD file, while the output is a fully routed NCD file. Review reports are generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design: Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

Verilog HDL Lab Manual Dated: 29/04/2011 Process properties Constraints Source files Synthesis and again implementation of the design is being made until design requirements are met. Timing verification of the design can be made at different points in the design flow as follows: i) Run static timing analysis at the following points in the design flow: After Map. After Place and Route. ii) Running Timing Simulations at the following points in the design flow: After Map (for a partial timing analysis of CLB and IOB delays). After Place and Route (for full timing analysis of block and net delays).

Program onto FPGAProgramming on the Xilinx device can be made as follows: Creation of a programming file (BIT) to program FPGA. Generate a PROM, ACE, JTAG file for debugging or to download to the device. Use iMPACT to program the device through programming cable. Xilinx FPGA, as an SRAM-based programmable PLD, must be configured with the configuration bitstream. The configuration bitstream is generated from the fully routed NCD file, by means of a BitGen program. The output of BitGen is a binary file with the .BIT extension that can be formatted for different PROM devices.

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

Verilog HDL Lab Manual

Dated: 29/04/2011

EXPERIEMENT NO. 1Simulation using all the modeling styles and Synthesis of all the logic gates using Verilog HDL AIM:Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. then, Synthesize each one of them on two different EDA tools.

Electronics Design Automation Tools used:i) 3.1 (includes Model Spectrum Synthesis Tool) ii) Xilinx Project Navigator 8.1 (Includes all Simulation to Implementation to download onto FPGA). FPGA Advantage Sim the simulation steps in the tool and Leonardo flow from design

Block Diagram:

A

And, Nand, Or, Nor, Xor, Xnor

C

B

Truth table:And Gate: A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1 Nand Gate: A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0 A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1 Nor Gate: Or Gate:

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

Verilog HDL Lab Manual Xor Gate: A B 0 0 0 1 1 0 1 1 Xnor Gate: A B Y 0 0 1 0 1 0 1 0 0 1 1 1

Dated: 29/04/2011

Y 0 1 1 0

Boolean Equation:And Gate: Y = (A.B) Nand Gate: Y = (A.B) Xor Gate: Y = A.B + A.B Or Gate: Y = (A + B) Nor Gate: Y = (A+B) Xnor Gate: Y = A.B + A.B

Verilog Code (In different modeling styles):And Gate (In Dataflow, behavioral Modeling): Module andg(a,b,c); input a,b; output c; assign c = a & b; endmodule Module andg1(a,b,c); input a,b; always(a,b) begin if (a==1b0 or b == 1b0) c = 1b0; else if (a==1b0 or b == 1b1) c = 1b0; else if (a==1b1 or b == 1b0) c = 1b0; else if (a==1b1 or b == 1b1) c = 1b1; end endmodule

Or gate(Dataflow, behavioral modeling):Module org (a,b,c); input a,b; output c; assign c = a | b; endmodule

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.) parag.vlsi@gmail.com

Verilog HDL Lab ManualNand Gate (In Dataflow modeling): Module nandg (a,b,c); input a,