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Verilog HDL Verilog HDL (Behavioral Modeling) (Behavioral Modeling) Bilal Saqib

Verilog HDL (Behavioral Modeling)

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Verilog HDL (Behavioral Modeling). Bilal Saqib. Behavioral Modeling. Structured Procedures. Procedural Blocks are constructed from the following components. Procedural Assignment Statements High-Level Constructs. Procedural Blocks. Procedural Assignments. - PowerPoint PPT Presentation

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Page 1: Verilog  HDL (Behavioral Modeling)

Verilog HDLVerilog HDL(Behavioral Modeling)(Behavioral Modeling)

Bilal Saqib

Page 2: Verilog  HDL (Behavioral Modeling)

Behavioral ModelingBehavioral Modeling

Page 3: Verilog  HDL (Behavioral Modeling)

Structured ProceduresStructured Procedures

Page 4: Verilog  HDL (Behavioral Modeling)

Procedural BlocksProcedural Blocks

Procedural Blocks are constructed from the following components.◦Procedural Assignment Statements◦High-Level Constructs

Page 5: Verilog  HDL (Behavioral Modeling)

Procedural AssignmentsProcedural Assignments

Page 6: Verilog  HDL (Behavioral Modeling)

Procedural Execution ControlProcedural Execution Control

Execution of Procedural Blocks can be specified in different ways◦Simple Delays: #<delay>

Specify delay before and after execution for a number of time steps.

◦Edge-Sensitive Controls: always @ (<edge><signal>) Execution occurs only at a signal edge. Optional

keywords “posedge” or “negedge” can be used to specify signal edge for execution.

Page 7: Verilog  HDL (Behavioral Modeling)

NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments

Page 8: Verilog  HDL (Behavioral Modeling)

NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments

Page 9: Verilog  HDL (Behavioral Modeling)

Conditional Statements: if elseConditional Statements: if else

Page 10: Verilog  HDL (Behavioral Modeling)

Conditional Statements: caseConditional Statements: case

Page 11: Verilog  HDL (Behavioral Modeling)

casex and casezcasex and casez

Page 12: Verilog  HDL (Behavioral Modeling)

Looping Statements: repeat

Page 13: Verilog  HDL (Behavioral Modeling)

Looping Statements: while

Page 14: Verilog  HDL (Behavioral Modeling)

Looping Statements: forever

Page 15: Verilog  HDL (Behavioral Modeling)

Looping Statements: for