Verilog-HDL Tutorial (7)

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  1. 1. 1 Verilog-HDL DE0(7) (2) 3, July, 2013
  2. 2. 2 () () () : 3 (En==1) Q0 Q1 Q2 En==1 Out=2'b01 En==1 Out=2'b10 En==1 Out=2'b00 En==0 Out=2'b00 En==0 Out=2'b01 En==0 Out=2'b10 Reset Out=2'b00
  3. 3. 3 DE0 () () : 3 (SW[0]==1) Q0 Q1 Q2 SW[0]==1 LEDG=2'b01 SW[0]==1 LEDG=2'b10 SW[0]==1 LEDG=2'b00SW[0]==0 LEDG=2'b00 SW[0]==0 LEDG=2'b01 SW[0]==0 LEDG=2'b10 Reset LEDG=2'b00 Reset -> BUTTON[0]: (:0, : 1) Out -> LEDG[1:0]: (:1, :0) En -> SW[0]: (:1, :0)
  4. 4. 4 ! (DE0TerasicCD-ROM ) DE0CD-ROM Demonstrations "DE0_Top" C:verilogDE0_tutorial_7_1
  5. 5. DE0_TOP.qpf Quartus II 5 Pin Planner
  6. 6. Verilog-HDL 6 Verilog-HDL
  7. 7. 7 Verilog-HDL (1) 2() () () : 3 (SW[0]==1) 00 01 10 SW[0]==1 LEDG=2'b01 SW[0]==1 LEDG=2'b10 SW[0]==1 LEDG=2'b00SW[0]==0 LEDG=2'b00 SW[0]==0 LEDG=2'b01 SW[0]==0 LEDG=2'b10 Reset LEDG=2'b00
  8. 8. 8 Verilog-HDL (2) 00 01 10 SW[0]==1 LEDG=2'b01 SW[0]==1 LEDG=2'b10 SW[0]==1 LEDG=2'b00 SW[0]==0 LEDG=2'b00 SW[0]==0 LEDG=2'b01 SW[0]==0 LEDG=2'b10 module DE0_TOP(CLOCK_50, SW, BUTTON, LEDG ); endmodule Reset LEDG=2'b00 DE0_TOP
  9. 9. 9 Verilog-HDL (3) 00 01 10 module DE0_TOP(CLOCK_50, SW, BUTTON, LEDG ); input CLOCK_50; input [9:0]SW; input [2:0]BUTTON; output [9:0]LEDG; () reg [1:0]LEDG; reg [1:0]state; endmodule LEDG DE0_TOP SW[0]==1 LEDG=2'b00 SW[0]==0 LEDG=2'b00 SW[0]==0 LEDG=2'b01 SW[0]==0 LEDG=2'b10 SW[0]==1 LEDG=2'b01 SW[0]==1 LEDG=2'b10 Reset LEDG=2'b00
  10. 10. 10 Verilog-HDL (4) 00 01 10 module DE0_TOP(CLOCK_50, SW, BUTTON, LEDG ); input CLOCK_50; input [9:0]SW; input [2:0]BUTTON; output [9:0]LEDG; () reg [1:0]LEDG; reg [1:0]state; always@( posedge CLOCK_50 or negedge SW[0]) begin if( SW[0] == 1'b0)begin LEDG