Verilog-HDL Tutorial (11)

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  • 1

    Verilog-HDL DE0(11) PS2

    4, July, 2013

  • PS/2

    LSB 1

    F0

    V DE03.3V

    2

  • PS/2

    3

    CLOCK

    DATA

    (0) Bit 0

    Bit 1

    Bit 2

    Bit 3

    Bit 4

    Bit 5

    Bit 6

    Bit 7

    (1)

    0 0 1 0 1 1 1 1 0 0 1

    (8) (LSB) (0111_1010)

    1 1, 0

    CLOCKDATA Tck=30us50us,10.0Hz16.6Hz

  • , CLOCK 1usec111000 1usec.

    4

    CLOCK

    DATA

    PS2_KBCLK

    CLOCK

    1usec 1MHz 1 1 1 0 0 0

    catch_negedge[5:0]

  • PS2

    5

    CLOCK_50

    RESET_N

    CLK1MHz CLK1MHz

    PS2_KBCLK

    PS2_KBDAT

    LEDG

    RESET_N

    10

    1MHz (Gen_CLK1MHz)

    PS2 (DE0_TOP)

  • 6

    Start Bit Data

    Bit0 Data Bit1 Data

    Bit2 Data Bit3 Stop

    Bit Parity Bit Data

    Bit7 Data Bit6 Data

    Bit5 Data Bit4

    Reset LEDG

  • 7

    ! (DE0TerasicCD-ROM )

    DE0CD-ROM Demonstrations "DE0_Top" C:verilogDE0_tutorial_7_1

  • DE0_TOP.qpfQuartus II

    8

    Pin Planner

  • Verilog-HDL

    9

    Verilog-HDL

  • Verilog-HDL

    10

  • 11

    Verilog-HDL ()

  • LEDG (JISPS2)

    12

    k

    0 1 0 0 0 0 1 0

    12, =1

    =0

  • 13

    0 1 0 0 0 0 1 0 16 0x42 k

    F0 (LEDG )

    (101)

  • PS/27LED PS/2Verilog-HDL, ,

    14