Verilog HDL - 2. Introduce to Verilog HDL

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Text of Verilog HDL - 2. Introduce to Verilog HDL

The Verilog HDL

Th.S Nguyn Th Hong B mn Vin thng, Khoa K Thut in T Trng i hc Cng Nghip TP. H Ch Minh

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

What is HDLs ? HDLs - Hardware Description Languages HDL : a language used to describe a digital system

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

The Verilog HDLVerilog is convenient, device-independent representation of digital logic

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

The Verilog HDL (cont.) Originally a modeling language for a very efficient eventdriven digital logic simulator Later pushed into use as a specification language for logic synthesis Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other) Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages Combines structural and behavioral modeling styles

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog : Synthesis and Simulation Simulation / synthesis Design / Testbench

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Structural Modeling When Verilog was first developed (1984) most logic simulators operated on netlists Netlist: list of gates and how theyre connected A natural representation of a digital logic circuit Not the most convenient way to express test benchesM.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Behavioral Modeling

A much easier way to write testbenches Also good for more abstract models of circuitsEasier to write Simulates faster

More flexible Provides sequencing Verilog succeeded in part because it allowed both the model and the testbench to be described together

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog - overview

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog Module definitionmodule and2(A,B,OUT); and2(); Input A; Input B; Output OUT; assign OUT=A&B;//your comment endmodule

and2

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog Port declaration

To make code easy to read, use self-explanatory port names For the purpose of conciseness, use short port names In vector port declaration, MSB can be smaller index. e.g. output [0:3] result (result[0] is the MSB)M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog Examples not2 module module not2 (a , b); input a; output b; assign b = ~a; endmodule or2 module module or2 (in_a , in_b , out); input in_a; input in_b; output out; assign out = in_a | in_b; endmodule and2 module; module and2 (in_a , in_b , out); input in_a; input in_b; output out; assign out = in_a & in_b; endmodule nand2 module module nand2 (in_a , in_b , out); input in_a; input in_b; output out; assign out = ~ (in_a & in_b); endmodule The Verilog HDL

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

Verilog Hierarchical Module

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Top-Level ALU Declaration

Wiring Example 1 and2 module module and2 (a , b , c) input a; input b; output c; assign c = a & b; endmodule and3 module s dng module and2 module and3 (x , y , z , t ) input x; input y; input z; output t; wire temp; and2 u1(.a(x) , .b(y) , .c(temp) ); and2 u2(.a(temp) , .b(z) , .c(t) ); endmodule

Wiring Example 2 or2 module module or2 (in_a , in_b , out) endmodule or3 module s dng module or2 module or3 (in_x , in_y , in_z , out3 )

endmodule

More on Module Interconnection

Problems Cho module mux 2 to 1 (mux2_1.v), vit module mux4 to 1 cu to t hai mux 2 to 1 nh hnh sau

Verilog syntax (1)Numbers size is the size in bits base can be b(binary), o(octal), d(decimal), or h(hexadecimal) value is any legal number in the selected base, including x and z Default value is 32 bits decimal number. Example: 1b1, 1b0, 0 8b10000111 or 8b1000_0111 8d135 8h87 8bxxxx_xxxx 8bzzzz_zzzzM.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog syntax (1A)Example:a[2:0] = 3d9; //a=? b[3:0] = 4d18; //b=?

Example:a[5:0] = 3d19; //a[0]=? ,a[1]=? ,a[5]=?

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog syntax (2)Identifiers Identifiers are user-defined words for variables, module names, block names and instance names. Syntax Allowed symbols: ABCDE . . . abcdef. . . 1234567890 _$ Not allowed: anything else especially: - & # @ Example adder // use underscores to make your meaning by_8_shifter // identifiers more meaningful _ABC_ /* is not the same as */ _abc_ read_ // is often used for NOT Read * Identifiers in Verilog are case-sensitive.M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog Operators(1)Arithmetic Operators module adder (a, b, s); These perform arithmetic operations. parameter n = 7; input [n:0] a, b; The + and - can be used as either sign (-z) output [n+1:0] s; or operator (x-y) . assign s = a + b; Operators + (addition) endmodule - (subtraction) * (multiplication) / (division) % (modulus) Does synthesis tool support?

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog Operators(2)Bit-wise Operators Bit-wise operators do a bit-by-bit comparison between two operands. Operators ~ (bitwise NOT) & (bitwise AND) | (bitwise OR) ^ (bitwise XOR) ~^ or ^~ (bitwise XNOR) Example module and2 (a, b, c) input [1:0] a, b; output [1:0] c; c[0] = a[0] & b[0] assign c = a & b; c[1] = a[1] & b[1] endmoduleM.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

The Verilog HDL

Verilog Operators(3) Relational Operators Relational operators compare two operands and return a single bit 1 or 0. Operators < (less than) (greater than) >= (greater than or equal to) == (equal to) != (not equal to)M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

module and_or (a, b, sel, f); input a, b, sel; output f; reg f; always @ (a or b or sel) if (sel == 1'b1) f = a & b; else f = a | b; endmodule

The Verilog HDL

Verilog Operators(4) Logical Operators Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for single bit operands. They can work on expressions groups of bits, and treat all values that are nonzero as 1. Operators ! (logical NOT) && (logical AND) || (logical OR)M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

module and_or (a, b, sel1, sel2, f); input a, b; input sel1, sel2; output f; reg f; always @ (a or b or sel1 or sel2) if (sel1 == 1'b1 && sel2 == 1'b1) f = a & b; else f = a | b; endmodule

The Verilog HDL

Verilog Operators(5) Reduction Operators Reduction operators operate on all the bits of an operand vector and return a single-bit value. These are the unary (one argument) form of the bit-wise operators above. Example module chk_zero (a, z); Operators& (reduction AND) | (reduction OR) ~& (reduction NAND) ~| (reduction NOR) ^ (reduction XOR) ~^ or ^~ (reduction XNOR) input [2:0] a; output z; assign z = ~| a; endmodule

z = ~ ( a[0] | a[1] | a[2] ) a=3b010 => z=~(0 | 1 | 0)=0The Verilog HDL

M.E Hoang Nguyen, Telecommunications Department Ho Chi Minh City University of Industry, 2011

Verilog Operators(6) Shift Operators Shift operators shift the first operand by the number of bits specified by the second operand. Vacated positions are filled with zeros for both left and right shifts (There is no sign extension). Operators > (shift right) Example assign c = a