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The Verilog HDL
Th.S Nguyễn Thế Hoàng
Bộ môn Viễn thông, Khoa Kỹ Thuật Điện Tử
Trường đại học Công Nghiệp TP. Hồ Chí Minh
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
What is HDLs ?• HDLs - Hardware Description Languages • HDL : a language used to describe a digital system
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
The Verilog HDL
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
•Verilog is convenient, device-independent representation of digital logic
The Verilog HDL (cont.)
• Originally a modeling language for a very efficient event-driven digital logic simulator
• Later pushed into use as a specification language for logic synthesis
• Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other)
• Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages
• Combines structural and behavioral modeling styles
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog : Synthesis and Simulation
• Simulation / synthesis• Design / Testbench
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Structural Modeling
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• When Verilog was first developed (1984) most logic simulators operated on netlists
• Netlist: list of gates and how they’re connected
• A natural representation of a digital logic circuit
• Not the most convenient way to express
test benches
Behavioral Modeling
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• A much easier way to write testbenches• Also good for more abstract models of circuits
– Easier to write– Simulates faster
• More flexible• Provides sequencing• Verilog succeeded in part because it allowed both
the model and the testbench to be described together
Verilog - overview
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog – Module definition
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
module and2();
endmodule
and2
module and2(A,B,OUT);Input A;Input B;Output OUT;
endmodule
module and2(A,B,OUT);Input A;Input B;Output OUT;
assign OUT=A&B;//your comment
endmodule
Verilog – Port declaration
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
To make code easy to read, use self-explanatory port names For the purpose of conciseness, use short port names In vector port declaration, MSB can be smaller index. e.g. output [0:3] result (result[0] is the MSB)
Verilog – Examples
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
not2 modulemodule not2 (a , b);input a;output b;assign b = ~a;endmodule
and2 module;module and2 (in_a , in_b , out);input in_a; input in_b;output out;
assign out = in_a & in_b;endmodule
or2 modulemodule or2 (in_a , in_b , out);input in_a; input in_b;output out;
assign out = in_a | in_b;endmodule
nand2 modulemodule nand2 (in_a , in_b , out);input in_a; input in_b;output out;
assign out = ~ (in_a & in_b);endmodule
Verilog – Hierarchical Module
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Top-Level ALU Declaration
Wiring Example 1 and2 modulemodule and2 (a , b , c)input a; input b;output c;
assign c = a & b;endmodule
and3 module sử dụng module and2module and3 (x , y , z , t )input x; input y; input z;output t;
wire temp;and2 u1(.a(x) , .b(y) , .c(temp) );and2 u2(.a(temp) , .b(z) , .c(t) );
endmodule
Wiring Example 2 or2 module
module or2 (in_a , in_b , out)
endmodule
or3 module sử dụng module or2
module or3 (in_x , in_y , in_z , out3 )
endmodule
More on Module Interconnection
Problems
Cho module mux 2 to 1 (mux2_1.v), viết module mux4 to 1 cấu tạo từ hai mux 2 to 1 như hình sau
Verilog – syntax (1)
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Numbers<size>’<base><value> size is the size in bits base can be b(binary), o(octal), d(decimal), or h(hexadecimal) value is any legal number in the selected base, including x and z Default value is 32 bits decimal number.Example: 1’b1, 1’b0, 0 8’b10000111 or 8’b1000_0111 8’d135 8’h87 8’bxxxx_xxxx 8’bzzzz_zzzz
Verilog – syntax (1A)Example:
a[2:0] = 3’d9; //a=?
b[3:0] = 4’d18; //b=?
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Example:a[5:0] = 3’d19; //a[0]=? ,a[1]=? ,…a[5]=?
Verilog – syntax (2)
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
IdentifiersIdentifiers are user-defined words for variables, module names, block names and instance names. Syntax
Allowed symbols: ABCDE . . . abcdef. . . 1234567890 _$ Not allowed: anything else especially: - & # @
Example adder // use underscores to make your meaning by_8_shifter // identifiers more meaningful _ABC_ /* is not the same as */ _abc_ read_ // is often used for NOT Read* Identifiers in Verilog are case-sensitive.
Verilog – Operators(1)
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Arithmetic Operators These perform arithmetic operations. The + and - can be used as either sign (-z) or operator (x-y) .Operators
+ (addition)- (subtraction)* (multiplication)/ (division)% (modulus)
Does synthesis tool support?
module adder (a, b, s); parameter n = 7; input [n:0] a, b; output [n+1:0] s;
assign s = a + b;
endmodule
Verilog – Operators(2)
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Bit-wise Operators Bit-wise operators do a bit-by-bit comparison between two operands.Operators
~ (bitwise NOT)& (bitwise AND)| (bitwise OR)^ (bitwise XOR)~^ or ^~ (bitwise XNOR)
Examplemodule and2 (a, b, c)input [1:0] a, b;output [1:0] c;assign c = a & b;endmodule
c[0] = a[0] & b[0]c[1] = a[1] & b[1]
Verilog – Operators(3)• Relational Operators
• Relational operators compare two operands and return a single bit 1 or 0.
• Operators
< (less than)
<= (less than or equal to)
> (greater than)
>= (greater than or equal to)
== (equal to)
!= (not equal to)
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
module and_or (a, b, sel, f); input a, b, sel; output f; reg f; always @ (a or b or sel) if (sel == 1'b1) f = a & b; else f = a | b;endmodule
Verilog – Operators(4)• Logical Operators• Logical operators return a single bit 1 or
0. They are the same as bit-wise operators only for single bit operands. They can work on expressions groups of bits, and treat all values that are nonzero as “1”.
• Operators
! (logical NOT)
&& (logical AND)
|| (logical OR)
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
module and_or (a, b, sel1, sel2, f); input a, b; input sel1, sel2; output f; reg f; always @ (a or b or sel1 or sel2) if (sel1 == 1'b1 && sel2 == 1'b1) f = a & b; else f = a | b;endmodule
Verilog – Operators(5)• Reduction Operators• Reduction operators operate on all the bits of an
operand vector and return a single-bit value. These are the unary (one argument) form of the bit-wise operators above.
• Operators& (reduction AND)
| (reduction OR)
~& (reduction NAND)
~| (reduction NOR)
^ (reduction XOR)
~^ or ^~ (reduction XNOR)M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Example module chk_zero (a, z); input [2:0] a; output z; assign z = ~| a; endmodule
z = ~ ( a[0] | a[1] | a[2] )a=3’b010 => z=~(0 | 1 | 0)=0
Verilog – Operators(6)• Shift Operators• Shift operators shift the first operand by the number of bits
specified by the second operand. Vacated positions are filled with zeros for both left and right shifts (There is no sign extension).
• Operators– << (shift left)– >> (shift right)
• Example – assign c = a << 2; – // c = a shifted left 2 bits; vacant positions are filled with 0’s – // a = 8’b1111_0000, c = 8’b1100_0000
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog – Operators(6)• Concatenation Operator• The concatenation operator combines two or more operands to
form a larger vector.• Operators
– { } (concatenation)• Example
– wire cout;
– wire [1:0] a, b, s;
– wire [2:0] x;
– wire [3:0] y;
– assign x = {1’b0, a}; // x[2]=0, x[1]=a[1], x[0]=a[0]
– assign y = {a, b}; // y[3]=a[1], y[2]=a[0], y[1]=b[1], y[0]=b[0]
– assign {cout, s} = a + b; // Concatenation of a result
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog – Operators(6A)Example 1:
a[3:0] = 4’b1011;
b[3:0] = 4’b1100;
Wire y;
assign y = {a , b}; //y=?
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Example 2:a[7:0]=8’b10100011; b[7:0]=8’b11001101;wire [7:0] result;wire c;assign {c,result}=a+b; //c = ?,result=?
Example 3:a[7:0]=8’b10100011; assign a={a[3:0],a[7:4]}; //a = ?
Example 4:a[7:0]=8’b10100011; wire [7:0] b,c,d;assign b={a[7:4],1’b0}; //b = ?assign c={1’b1, a[7:4]}; //c = ?assign d={a[7:1],1’b0}; //d = ?
Verilog – Operators(7)• Replication Operator• The replication operator makes multiple copies of an item.• Operators
– {n{item}} (n fold replication of an item)• Example
wire [1:0] a, b;
wire [3:0] x;
assign x = {2{1’b0}, a}; // Equivalent to x = {0, 0, a[1], a[0]}
x[3] x[2] x[1] x[0]
assign y = {2{a}, 3{b}}; //Equivalent to y = {a, a, b, b, b}
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog – Operators(7A)Example 1:
a[1:0] = 2’b01;
b[2:0] = 3’b110;
wire [9:0] y;
assign y = {2{a} , 3{b} }; //y=?
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Example 2:
a[3:0]=4’b1011; wire [7:0] y;assign y={4{a[3]} , a}; //y = ?
Verilog – Operators(8)• Conditional Operator: “?”• Conditional operator is like those in C/C++. They
evaluate one of the two expressions based on a condition. It will synthesize to a multiplexer (MUX).
• Operators– (cond) ? (result if cond true) : (result if cond false)
• Exampleassign a = (g ) ? x : y;
assign a = (inc == 2) ? a +1 : a -1;
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
1
0
g
y
x
aMUX
Verilog – Operators(8A)
Example :a[1:0] = 2’b01;b[2:0] = 3’b110;wire [2:0] y,z;assign y = (a==1)?9:5; //y=?assign z = (b==2)?3:(a==1)?2:1; //z=?
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog – Operators(9)
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog – Operators(10)• Bit-Selects
• Bit-selects and part-selects are a selection of a single bit and a group of bits, respectively, from a wire, reg or parameter vector using square brackets “[ ]”.
• Syntax
– variable_name [index]
– variable_name [msb:lsb]
• Example
– wire [7:0] a, b;
– wire [3:0] ls;
– wire c;
– assign c = a[7] & b[7]; // bit-selects
– assign ls = a[7:4] + b[3:0]; // part-selects
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Two Main Components of Verilog
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• Concurrent, event-triggered processes (behavioral)– Initial and Always blocks– Imperative code that can perform standard data manipulation
tasks (assignment, if-then, case)– Processes run until they delay for a period of time or wait for a
triggering event• Structure
– Verilog program build from modules with I/O interfaces– Modules may contain instances of other modules– Modules contain local signals, etc.– Module configuration is static and all run concurrently
Two Main Data Types
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• Wires represent connections between things– Do not hold their value– Take their value from a driver such as a gate or other module– Cannot be assigned in an initial or always block
• Regs represent data storage – Behave exactly like memory in a computer– Hold their value until explicitly assigned in an initial or always block– Never connected to something– Can be used to model latches, flip-flops, etc., but do not
correspond exactly– Shared variables with all their attendant problems
Two Main Data Types
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• Wires represent connections between things– Use by assign statement, can not assigned in always/initial block
wire a;
assign a = 2; //correct
always @(a) begin
assign a = 2; //incorrect
a=2; //incorrect
end
Two Main Data Types
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• Regs represent data storage – Can be assigned in always/initial block
reg a;
assign a = 2; //incorrect
always @(a) begin
assign a = 2; //incorrect
a=2; //correct
end
Four-valued Data
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• Verilog’s nets and registers hold four-valued data• 0, 1
– Obvious
• Z– Output of an undriven tri-state driver– Models case where nothing is setting a wire’s value
• X– Models when the simulator can’t decide the value– Initial state of registers– When a wire is being driven to 0 and 1 simultaneously– Output of a gate with Z inputs
Structural Modeling
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• Nets and Registers
• Modules and Instances
• Gate-level Primitives
• Delays on Primitive Instances
• A Sequential Primitive
• Continuous Assignment
Behavioral Modeling
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
• Initial and Always Blocks
• Procedural Assignment
• Imperative Statements
• Blocking vs. Nonblocking
Structual Modeling
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Nets and Registers
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Wires and registers can be bits, vectors, and arrays
wire a; // Simple wire
tri [15:0] dbus; // 16-bit tristate bus
tri #(5,4,8) b; // Wire with delay
reg [-1:4] vec; // Six-bit register
trireg (small) q; // Wire stores a small charge
integer imem[0:1023]; // Array of 1024 integers
reg [31:0] dcache[0:63]; // A 32-bit memory
Gate-level Primitives
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Verilog provides the following:
and nand // logical AND/NAND
or nor //logical OR/NOR
xor xnor //logical XOR/XNOR
buf not //buffer/inverter
bufif0 notif0 //Tristate with low enable
bifif1 notif1 //Tristate with high enable
Delays on Primitive Instances
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Ho Chi Minh City University of Industry, 2011The Verilog HDL
Instances of primitives may include delays
`timescale 1 ps / 1 ps //define simulation time unit
buf b1(a, b); // Zero delay
buf #3 b2(c, d); // Delay of 3
buf #(4,5) b3(e, f); // Rise=4, fall=5
buf #(3:4:5) b4(g, h); // Min-typ-max delay
Ex : Led 7 segments display module
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Led 7 segments decoder module
b3
S6
b2
b1
b0
BCD7SegBCD7Seg
S5
S4
S3
S2
S1
S0
Led 7 segments display module
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Truth table
b3
S6
b2
b1
b0
BCD7SegBCD7Seg
S5
S4
S3
S2
S1
S0
BOOLEAN FUNCTIONBOOLEAN FUNCTION
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
S[0] = B3 B2 B1 B0 + B2 B1 B0
B B
B2 B1 B0
3 2
B1B0
S[0]
XX
XX
X1
X1
00 01 11 10
00
01
11
10 XX
XX
X1
X1
00 11 10
00
01
11
10
B3 B2 B1 B0
Using KARNAUGH Map to minimal expression of a boolean function
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Boolean Function
Verilog code – Structural Style
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
file : bcd7seg_struc.vmodule bcd7seg(b,S); input [3:0] b; output [6:0] S; wire [6:0] S;
assign S0=(b0&(!b1)&(!b0)) | ((!b3)&(!b2)&(!b1)&(b0));assign S1=(b2&(!b1)&b0) | (b2&b1&(!b0));assign S2=(!b2)&b1&(!b0);assign S3=((!b3)&(!b2)&(!b1)&b0) | (b2&(!b1)&(!b0)) | (b2^b1&b0);assign S4=b0 | (b2&(!b1));assign S5=(b1&b0) | ((!b2)&b1) | ((!b3)&(!b2)&b0);assign S6=(b2&b1&b0) | ((!b3)&(!b2)&(!b1)); endmodule
Behavioral Modeling
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Initial and Always Blocks
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Ho Chi Minh City University of Industry, 2011The Verilog HDL
Basic components for behavioral modeling
initial
begin
// … your code here …
end
//Runs when simulation starts
//Terminates when control
//reaches the end
//Good for providing stimulus
always
begin
//… your code here …
end
//Runs when simulation starts
//Restarts when control
//reaches the end
//Good for modeling/specifying
// hardware
Initial and Always
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Run until they encounter a delayinitial begin #10 a = 1; b = 0; //a,b must be a regs #10 a = 0; b = 1;end
or a wait for an eventalways @(posedge clk)
q = d; //q must be a regs
always begin wait(i); a = 0; //a must be a regswait(~i); a = 1;
end
Conditional statement
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If/else statement
if (select == 1) y = a;else y = b;
case/endcase statement
case (op) 2’b00: y = a + b; //if (op==0) then y = a+b 2’b01: y = a – b; 2’b10: y = a ^ b; default: y = ‘hxxxx;endcase
If/else vs case
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
if…else case
For Loop
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Ho Chi Minh City University of Industry, 2011The Verilog HDL
reg [3:0] i, output;
for ( i = 0 ; i <= 3 ; i = i + 1 ) begin
output = i;
#10;
end
reg [3:0] i, output;
begin
output = i;
#10;output = i;
#10;output = i;
#10;output = i;
#10;
end
While Loop
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Ho Chi Minh City University of Industry, 2011The Verilog HDL
reg [3:0] i, output;
i=0;
while ( i <= 3) begin
output = i;
#10;
i=i+1;
end
reg [3:0] i, output;
begin
output = i;
#10;output = i;
#10;output = i;
#10;output = i;
#10;
end
Ex : mux 4 to 1 module
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Mux 4 to 1 module
i3
i2
i1
i0
Out
Sel[1:0]
module mux4_1 (i0,i1,i2,i3,sel,out);input i0,i1,i2,i3;output reg out;input [1:0] sel;always @(sel or i0 or i1 or i2 or i3)begin
if(sel==0) out=i3;else if(sel==1) out=i2;else if(sel==2) out=i1;else out=i0;
endendmodule
Led 7 segments display module
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
Truth table
b3
S6
b2
b1
b0
BCD7SegBCD7Seg
S5
S4
S3
S2
S1
S0
Verilog code – Behavioral Style
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
file : bcd7seg_behav.vmodule bcd7seg(b,S); input [3:0] b; output [6:0] S; reg [6:0] S;Always @(b) begin
case (b)4’h0: S= 7’b1000000; 4’h1: S= 7’b1111001;4’h2: S= 7’b0100100;…4’h9: S= 7’b0010000;default : S = 7’bxxxxxxx;
endcaseendendmodule
M.E Hoang Nguyen, Telecommunications Department
Ho Chi Minh City University of Industry, 2011The Verilog HDL
References• [1] David Harris, Structural Design with Verilog,
2010• [2] Prof. Stephen A. Edwards, CS dept.,
Columbia University• [3] John F. Warkerly, Digital Logic Design:
Practice and Principles, 3rd Edition, Prentice Hall International Inc., 2002.
• [4] J. Bhasker, A Verilog HDL, Star Galaxy Publishing, 1999.
• [5] World of ASIC,www.asic.com
• Thực hiện mạch chuyển đổi số nhị phân 6bit thành hai số bcd-4bit
Problems