Verilog HDL Outline

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    - 1 -20052005 VLSI Training CourseVLSI Training Course

    Verilog HDL

    Teaching Assistant: Lien-Fei Chen ()

    Instructor: Prof. Yeong-Kang Lai

    Multimedia & Communication IC Design LabElectrical Engineering, National Chung Hsing University

    Fall, 2005

    - 2 -20052005 VLSI Training CourseVLSI Training Course

    Outline

    Introduction to Introduction to VerilogVerilog HDLHDLVerilog data types and modelsVerilog test benchIntroduction to Verilog-XL simulatorAnnotating SDF Timing

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    What is a Hardware Description Language ?

    High-level programming language with special constructs used to model the function of hardware logic circuitsThe special language constructs provides the ability to Describe the connectivity of the circuit Describe the functionality of a circuit Describe a circuit at various levels of abstraction Describe the timing of a circuit Express concurrency

    - 4 -20052005 VLSI Training CourseVLSI Training Course

    Why Use an HDL ?

    There are several benefits in using an HDL to describe your design Top-down methodology using synthesis

    Design at an implementation-independent, higher levelExplore design alternatives easilyFind problems eariler in the design cycleAutomate mapping of high-level descriptions to technology-specific implementations

    An HDL provides greater flexibilityRe-useChoice of tools, vendors

    An HDL provides the advantages of decades of software practices

    Faster design captureEasier to manage

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    - 5 -20052005 VLSI Training CourseVLSI Training Course

    What is Verilog HDL ?

    A hardware description language Verilog models digital electronic system Verilog lets you model at different levels of abstraction Verilog lets you develop tests to verify the functionality of the

    devices you model

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    A Brief History of Verilog

    1981 Gateway Design Automation released GenRads Hardware Description Language (GHDL)1983 Gateway released Verilog HDL1985 Enhanced simulator Verilog-XL released1989 Cadence bought Gateway1990 Cadence released Verilog to public domain1993 EE Times reported 85% designs submitted to ASIC foundries were designed and submitted using Verilog1995 Reviewed and adopted as IEEE standard 1364

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    - 7 -20052005 VLSI Training CourseVLSI Training Course

    Levels of Abstraction for VerilogHDL & VHDL

    vital

    System

    Algorithm

    RTL

    Logic

    Gate

    Verilog

    VHDL

    Synthesizable RTL Code

    BehavioralLevel

    BehavioralLevel

    RTLLevelRTL

    Level

    GateLevelGateLevel

    - 8 -20052005 VLSI Training CourseVLSI Training Course

    Levels of Abstraction for Verilog

    Models can be written with different levels of detailsThree main levels of abstraction in Verilog Behavioral

    Describes a system by the flow of data between its functional blocksSchedules assignments at functional boundaries only when necessary

    Register Transfer Level (RTL)Register Transfer Level (RTL)Describes a system by the flow of data and controls signals within and between functional blocksDefines the model in terms of cycles, based on a defined clock

    Structural (Gate-level)Models components by connecting primitives or low-level components (gates) for greater accuracy, especially in timingUses technology-specific, low-level components when mapping from an RTL description to a gate-level netlist, such as during synthesis

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    - 9 -20052005 VLSI Training CourseVLSI Training Course

    Behavioral and RTL (1/2)

    The behavioral/RTL description does not handle unknown and tristate inputs exactly as the structural implementation would, and has no propagation delays

    module mux2to1 (a, b, sel, out);input [7:0] a, b;input sel;output [7:0] out;reg [7:0] out;

    always @ (a or b or sel)begin

    if (sel == 1b1)out = a;

    elseout = b;

    endendmodule

    a

    bout

    sel

    - 10 -20052005 VLSI Training CourseVLSI Training Course

    Behavioral and RTL (2/2)

    Behavioral model The function of the logic is modeled using high level

    language constructs, such as @, while, wait, if/elseand case

    RTL model Based on clock RTL model must be accurate at the boundary of every

    clocked elements RTL level is appropriate for synthesis, so designers use RTL

    to mean the synthesizable subset of behavioral VerilogTestbenchs, or test fixtures, are typically modeled at the behavioral level.All behavior constructs are legal for testbenchs.

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    Overall Structure

    No glue logic within top module

    Top module

    - 12 -20052005 VLSI Training CourseVLSI Training Course

    Outline

    Introduction to Verilog HDLVerilogVerilog data types and modelsdata types and models VerilogVerilog operationsoperations VerilogVerilog data typesdata types VerilogVerilog modelsmodels

    Verilog test benchIntroduction to Verilog-XL simulatorAnnotating SDF Timing

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    - 13 -20052005 VLSI Training CourseVLSI Training Course

    Module Definition

    module MyCPU (clk, rst, data, address, result);input clk, rst;input [31:0] data, address;output [31:0] result;

    .

    .

    .

    .

    .

    .endmodule

    I/O port declarations

    Resource/variable declarations

    RTL modeling

    - 14 -20052005 VLSI Training CourseVLSI Training Course

    Value Set and Numbers

    Value set 0 logic zero or false condition 1 logic one or true condition x unknown or dont care logic value z high-impedance state

    Number representation base b, d, o ,h

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    Data Types (1/2)

    Signal nets wire, tri

    Wired nets wand, wor, triand, trior trireg tri0, tri1

    Supply nets supply0, supply1

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    Data Types (2/2)

    Registers reg

    Memories array of register variables

    Integers (32-bit) integer

    Time (64-bit) time

    Real numbers real

    Parameters parameter

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    Operators (1/2)

    Arithmetic operators +, 1, *, /, %

    Relational operators (0, 1, x) , =

    Equality operators (0, 1) ==, !=, ===, !==

    Logical operators (0, 1) &&, ||, !

    Bit-wise operators ~, &, |, ^, ~^, ^~

    - 18 -20052005 VLSI Training CourseVLSI Training Course

    Operators (2/2)

    Reduction operators (unary) &, |, ^, ~&, ~|, ~^, ^~

    Shift operators (fill with zeros)

    Conditional operator ?...:

    Concatenations {, }

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    - 19 -20052005 VLSI Training CourseVLSI Training Course

    Module Connectivity

    Order list

    Name

    module top ();

    wire [7:0] data, result;inv INV0 (data, result);

    endmodule

    module inv (in, out);input [7:0] in, out;

    out = ~in;endmodule

    module top ();

    wire [7:0] data, result;inv INV0 (.in(data),

    .out(result));endmodule

    module inv (in, out);input [7:0] in, out;

    out = ~in;endmodule

    Better !!!

    - 20 -20052005 VLSI Training CourseVLSI Training Course

    Parameters

    Use parameters to declare run-time constantsYou can use a parameter anywhere that you can use a literalParameters are local, known only to the module in which they are defined

    module mod (in1, in2, out);

    parameter cycle = 20, prop_del = 3,setup = cycle/2 prop_del,p1 = 8,x_word = 16bx,file = /usr1/jdough/design/mem_file.dat;

    ...wire [p1:0] w1; // a wire declaration using parameter

    ...endmodule

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    - 21 -20052005 VLSI Training CourseVLSI Training Course

    Overriding the Values of Parameters (1/2)

    module mod (in1, in2, out);

    parameter p1 = 8,real_constant = 2.039,x_word = 16bx,file = /usr1/jdough/design/mem_file.dat;

    ...endmodule

    module test;...mod I1 (.in1(in1), .in2(in2), .out(out));defparam

    I1.p1 = 6;I1.file = ../my_mem.dat;

    endmodule

    Defparam StatementDefparam Statement

    - 22 -20052005 VLSI Training CourseVLSI Training Course

    Overriding the Values of Parameters (2/2)

    module mod (in1, in2, out);

    parameter p1 = 8,real_constant = 2.039,x_word = 16bx,file = /usr1/jdough/design/mem_file.dat;

    endmodule

    module top;...mod #(5, 3.0, 16bx, ../my_mem.dat)

    I1 (.in1(in1), .in2(in2), .out(out));...

    endmodule

    Module Instance Parameter OverrideModule Instance Parameter Override

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    Register Arrays

    You can declare an array of registers in Verilog

    An array of the datatype reg is often called a memory

    You can use parameters to model memory size

    integer nums [7:0]; // array of 8 integer variablestime t_vals [3:0]; // array of 4 time variables

    reg [15:0] MEM [0:1023]; // 1K x 16-bit memory arrayreg [7:0] PREP [`hFFFE:`hFFFF]; // 2 x 8-bit memory array

    parameter WORDSIZE = 16;parameter MEMSIZE = 1024;reg [WORDSIZE-1:0] mem3 [MEMSIZE-1:0];

    - 24 -20052005 VLSI Training CourseVLSI Training Course

    Memory Addressing

    module mems;

    reg [7:0] mema [0:255]; // declare memory called memareg [7:0] mem_word; // temp register called mem_word

    ...initialbegin

    // Display contents of the 6th memory address$display(mema[5]);// Display the MSB of the 6th memory wordmem_word = mema[5];$displayb(mem_word[7]); // Display the MSB

    endendmodule

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    - 25 -20052005 VLSI Training CourseVLSI Training Course

    Behavioral Modeling

    Event-dri