Verilog-HDL Tutorial (13)

  • View
    40

  • Download
    3

Embed Size (px)

Text of Verilog-HDL Tutorial (13)

  • 1

    Verilog-HDL DE0(13) RS232C(Tx)

    1, August, 2013

  • RS232C (9600 bps)

    2

    (10)

    (8) LSB()

    (11)

    D0 D1 D2 D3 D7

    9600 bps = 9600 bit per second , 1( ) 9600bit

  • 9600bps -> 9600Hz

    3

    (10)

    (8) LSB()

    (11)

    D0 D1 D2 D3 D7

  • 50MHz (DE0) 9600Hz

    4

    9600Hz , 1= 1 /9600 = 0.04 [sec]

    9600Hz

    , 0.04 / 2 = 0.02 [sec] High Low

    50MHz 50 MHz , 1= 1 / 50x106 = 0.02x10-6 [sec]

    , 0.02 / (0.02 x 10-6) = 100,000 High Low

  • 8(8)PC : 9600bps, :1 , :

    (BUTTON[2]), 1

    5

    USB (BUFFALO) BSUSRC0605BS

    (amazon2011)

    (8)

    ()

  • RS232C

    6

    0000 0001 0010 0011 0100 0101

    1011 1010 1001 1000 0111 0110

    Reset UART_TXD

  • 7

    ! (DE0TerasicCD-ROM )

    DE0CD-ROM Demonstrations "DE0_Top" C:verilogDE0_tutorial_9_LEDG_Slide

  • DE0_TOP.qpfQuartus II

    8

    Pin Planner

  • Verilog-HDL

    9

    Verilog-HDL

  • 9600Hz

    10

  • Verilog-HDL

    11

  • Verilog-HDL

    12

    Gen_CLK9600Hz.v

  • RS232C

    13

  • Verilog-HDL (1)

    14

  • Verilog-HDL (2)

    15

  • Verilog-HDL (3)

    16

  • Verilog-HDL

    17

    RS232C_TX.v

  • DE0_Top.v

    18

  • 19

    OK

  • FPGAPC COM(RS232C) (Windowx XP)

    20 PCCOM7

  • FPGA

    21

  • RS232C VECTOR (http://www.vector.co.jp/soft/winnt/hardware/se411276.html)

    22

    PC

    : 9600, : 8, : : 1

  • PCFPGA RS232C

    23

  • RS232C

    24

    1. RS232C ()

    2.

    3. (11000101, 160xC5 )

    4. RS232C

  • RS232C

    : (115200bps, 14400bps) 9600bpsRS232C, PC

    25