Verilog-HDL Tutorial (14)

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  • 1

    Verilog-HDL DE0(14) CycloneM9K

    2, August, 2013

  • M9K AlteraFPGA Cyclone III(RAM:

    Random Access Memory): 19Kbit M9K RAM DE0FPGA (EP3C16)

    56M9K (504Kbit)

    2

  • M9K

    3

    8192 x 1 13 1 4096 x 2 12 2 2048 x 4 11 4 1024 x 8 10 8 1024 x 9 9 9 512 x 16 8 16 512 x 18 8 18 256 x 32 7 32 256 x 36 7 36

  • M9K ()

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    Single-port RAM Simple dual-port RAM

    True dual-port RAM

    Single-port ROM

    , Dual-port ROM, FIFO, Shift register

  • M9KROM

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  • M9K ROM()

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    clock address q

    ADR1

    DATA1

    ROM

    &

    ADR2

    DATA2

  • ROM1LEDG

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    READ ADR Set

    Reset r_adr

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    !

    (DE0TerasicCD-ROM )

    DE0CD-ROM Demonstrations "DE0_Top" C:verilogDE0_tutorial_14_M9K_basic

  • DE0_TOP.qpfQuartus II

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    Pin Planner

  • Verilog-HDL

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    Verilog-HDL

  • ROM

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    content.mif . content.mif

  • MIF

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    8 (3), () 10

    . 2 (binary)

    : ROM

  • MegaWizard

    14

  • Create a new custom megafunction variation

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  • ROM 1-PORT

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    Memory Compiler -> ROM: 1-PORT

    Verilog-HDL

    ROM_LEDG

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    (q)10 8

    M9K

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    Browse mif (ROM)

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    Files of type: MIF les (*.mif)

    content.mif

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    Instantiation template le

  • Yes

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  • , Instantiation template le

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    ROM_LEDG_inst.v

    Quartus II DE0_TOP.v

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    Verilog-HDL

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    OK

  • Compilation Report Project Navigator M9K

    28

    Project Navigator

  • FPGA

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  • 1MIF LEDG

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  • M9KRAM

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  • Sinple-port RAM

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    clock address data wren q

    ADR1

    DATA1

    Write

    Read RAM

    Read

    ADR2

    DATA2

    Write ON

    & Write OFF

  • RAM

    SW[9:4]: (6) SW[3:0]: (4) BUTTON[2]: LEDG[3:0]: RAM

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    !

    (DE0TerasicCD-ROM )

    DE0CD-ROM Demonstrations "DE0_Top" C:verilogDE0_tutorial_14_M9K_RAM

  • DE0_TOP.qpfQuartus II

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    Pin Planner

  • Verilog-HDL

    36

    Verilog-HDL

  • MegaWizard

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  • Create a new custom megafunction variation

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  • RAM: 1-PORT

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    Memory Compiler -> RAM: 1-PORT

    Verilog-HDL

    M9K_RAM

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    (q)4 64

    M9K

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  • ()

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    (RAM) blank ()OK RAM . , mif

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  • Instantiation Template File

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  • Instantiation Temple File DE0_TOP.v

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    M9K_RAM_inst.v

    Quartus II DE0_TOP.v

  • Verilog-HDL

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    OK

  • , Compilation Report M9K

    (64 x 4 = 256?)

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  • FPGA

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  • : 1111 LEDG1111 (000000)

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    : 000000 : 0000 LEDG

    : 0001 LEDG0001 (000000)

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    : 000001 LEDG (000001)

    : 0001 LEDG0001 (000001)

    : 000000 LEDG1111 (RAM)

  • M9K ROM RAM Single-Port

    ROM, LEDG

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