Verilog-HDL Tutorial (8)

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  1. 1. 1 Verilog-HDL DE0(8) (3) 3, July, 2013
  2. 2. 2 2 (: 18 x 21 = 378) 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 1 0 18 21 256+64+32+16+8+2=378 =1 =0 0
  3. 3. 3 LUT LUT n
  4. 4. 4 () 0, 1, 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 1 0 18 21 =1 =0 0 , 000010010 000100100 001001000 010010000 100100000
  5. 5. 5 1. TEMP. TEMP