Verilog-HDL Tutorial (4)

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  1. 1. 1 Verilog-HDL DE0(4) 12, June, 2013
  2. 2. 2 x_in y_in carry in carry out sum out x_in y_in carry in sum out carry out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
  3. 3. 3 n x0 x1 x2 y0 y1 y2 0 s0 s1 s2 s3 x2 x1 x0 +)y2 y1 y0 -------------- s3 s2 s1 s0
  4. 4. 4 C x0 x1 x2 y0 y1 y2 0 s0 s1 s2 s3 x2 x1 x0 +)y2 y1 y0 -------------- s3 s2 s1 s0 3
  5. 5. 5 ! (DE0TerasicCD-ROM ) DE0CD-ROM Demonstrations "DE0_Top" C:verilogDE0_tutorial_4
  6. 6. DE0_TOP.qpf Quartus II 6 Pin Planner
  7. 7. Verilog-HDL 7 Verilog-HDL
  8. 8. 8 Verilog-HDL
  9. 9. 9 Verilog-HDL ()
  10. 10. 10 () () ( ); ; full_adder fadr_inst_1
  11. 11. 11 SW[0] SW[1] SW[2] SW[3] SW[4] SW[5] 0 LEDG[0] LEDG[1] LEDG[2] LEDG[3] three_bit_adder fadr_inst_1 fadr_inst_2 fadr_inst_3 w[0] w[1] Verilog-HDL
  12. 12. 12 x[0] x[1] x[2] y[0] y[1] y[2] 0 s[0] s[1] s[2] s[3] x[2] x[1] x[0] +)y[2] y[1] y[0] ---------------------- s[3] s[2] s[1] s[0]
  13. 13. (1) 13 (Cyclone III) Settings...
  14. 14. 14 "EDA Tool Settings" "Simulation" "Tool name""ModelSim-Altera" "Format for output netlist""Verilog-HDL"
  15. 15. 15 (Quartus II) I/O "Full Compilation was succesful" OK
  16. 16. 16 Start Test Bench Template Writer
  17. 17. (1) 17 Settings "EDA Tool Settings" "Simulation" "Compile test bench" Test Benches
  18. 18. 18 "New" "Test bench and simulation les" File name ...
  19. 19. ( /simulation/modelsim .vt) 19 .vt
  20. 20. 20 DE0_TOP _vlg_tst Add OK
  21. 21. ModelSim(Altera) 21 ...
  22. 22. 22 Library DE0_TOP_vlg_tst Edit
  23. 23. 23 ()'() always "_"
  24. 24. 24 ()[(-1):0] (); : ()[()] : ()[():()]
  25. 25. 25 Recompile Simulate
  26. 26. Wave 26 Verilog-HDL SW[5]SW[0] LEDG[3:0] Objects Add Wave
  27. 27. 27 "Transcript" run 3ns
  28. 28. 28 SW[5]SW[3] Combine Signals Result Namex_in SW[5:3]
  29. 29. 29 SW[2]SW[0] y_in LEDG[3]LEDG[0] z_out 001+001=0010
  30. 30. 210 10 30 RadixUnsigned
  31. 31. 31 Quartus II "Full Compilation was succesful" OK
  32. 32. 32 FPGAPC 1. AC 2. USB PCFPGA 3.
  33. 33. 33 Programmer ()
  34. 34. 34 USB-Blaster, JTAG, Program Start Progress "100%(Successful)"
  35. 35. 35 (SW0SW5) , LEDG0LEDG3 3
  36. 36. 36 : (2-MUX) s x1 x2 y 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 2-MUX x1 x2 y s s 0 x1 , s 1 x2
  37. 37. 37 1 (2-MUX) Verilog-HDL FPGA , LED 2-MUX SW[0] SW[1] LEDG[0] SW[2]
  38. 38. 38 2 4-MUX Verilog-HDL , , DE0 2-MUX 2-MUX 2-MUX SW[0] SW[1] SW[2] SW[3] SW[4] SW[5] LEDG[0]