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Programmable Logic Architecture Programmable Logic Architecture Verilog HDL FPGA DesignVerilog HDL FPGA Design
Jason Tseng
Week 4
Abstract Abstract
Today’s class:Gate level modelingExamples
Gate-Level ModellingGate-Level Modelling Primitive logic gates (基本邏輯閘 ) are part of the Verilog
language. Build-in logic models (gate stands for one of the keywords): – Basic gates: and, nand, or, nor, xor, xnor (not xor) (see Fig.4-1)– Buffers and inverter gates: buf, not (see Fig. 4-2)– Three-state gates: bufif1 (buf if 1), bufif0 (buf if 0), notif1 (not
bufif1), notif0 (not bufif0) (see Fig.4-3)
• User-defined primitives (UDP) is defined as module instantiations Syntax: gate (drive_strength) #(delays) instance_name1(output,input_1,…,input_N), instance_name2(output,input_1,…,input_N);
– Instance name can be ignored.– Drive strength::=(pull-up,pull-down) defaults ::= (strong1,strong0) (see Table 3-1 for details)– Delay ::= #(rise,fall) or #rise and fall or #(rise and fall)
AND3
and_out in1 in2 in3
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
1 1 1 1
Or3
or_out in1 in2 in3
0 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
NAND2
nand_out in1 in2
1 0 0
1 0 1
1 1 0
0 1 1
nor_out in1 in2
1 0 0
0 0 1
0 1 0
0 1 1
NOR2
XOR
xor_out in1 in2
0 0 0
1 0 1
1 1 0
0 1 1
XNOR2
XOR2
xnor_out in1 in2
1 0 0
0 0 1
0 1 0
1 1 1
BUFIF1
bufif1_out in ctrl
z 0 0
0 0 1
z 1 0
1 1 1
BUFIF0
bufif0_out in ctrl
0 0 0
z 0 1
1 1 0
z 1 1
NOTIF1
notif1_out in ctrl
z 0 0
1 0 1
z 1 0
0 1 1
p.s.: inverse of bufif1
NOTIF0
notif0_out in ctrl
1 0 0
z 0 1
0 1 0
z 1 1
p.s.: inverse of bufif0
deco2_4
Com1_g
1-bit Comparator
Method 1: gate instantiation Method 2: bit-wise operator
2-bit Comparator (comp2_g)
mux2_1g
1-bit 2-1 multiplexer
Data Output from D-type Flip Flop using 2-1 Multiplexer
dff_sel
mux4_1gLogic Gates
1-bit 4-1 multiplexer (method 1)
mux4_1b_gbufif0 & bufif1
1-bit 4-1 multiplexer (method 2)