LECTURE III

INTRODUCTION TO HDL/VERILOG

• HDL: Hardware Description Languages (Verilog for this class) are a way in which digital circuits can be described in textual form.

• • Used in the design and testing of logic circuits. • It describes the logic circuit as represented by;• Logic Diagrams (Schematics)• Boolean Equations or• Truth Tables• Testing the circuit written in an HDL can be accomplished though logic

simulation. Waveforms of the circuit can be generated and checked for functional accuracy. This process is accomplished by creating a "Test Bench", also written with the HDL.

• Propagation delays can even be added for additional accuracy in testing.• • Currently there are two HDL's recognized by the IEEE (Institute of Electrical

and Electronic Engineers). These are Verilog and VHDL. VHDL is required for DOD (Department of Defense) projects and is significantly more complex to learn and use.

MODULES

• HDL programs consists of modules. Modules contain statements which define the circuit or a portion thereof.

• • Modules can call upon other modules to perform a portion of

their overall task. e.g. a multi-bit adder may consist of several half-adders. Rather than writing code for each half-adder which is needed, a single half-adder (sub)module can be written and called upon as many times as it is needed to construct the larger module. Every time this (sub)module is used, it is said to be instantiated within the larger module. In other words, each instance that the (sub)module is used, it is instantiated.

• Writing modules requires precise syntax and constructs. Module declarations MUST begin with the word module followed by a name and a list of ports.

• Ports are the inputs and outputs of the circuit described by the module. They may be listed in any order.

• e.g. module Simple_Circuit (A,B,C,D,E)• Module names (aka identifiers) may consist of alphanumeric characters and

underscores but MUST NOT begin with a number.• • Keywords are required to write your modules and must be written in lower case.

Examples include;• module indicates the beginning of a module• endmodule indicates the end of a module• inputindicates a port which inputs data output

indicates a port which outputs data• wire indicates a connection between gates• Certain gates are already defined by Verilog. These are known as primitives. e.g.• and an AND gate• or an OR gate• not an INVERTER

• Instantiations of gates consist of an optional gate name followed by the output and the input(s) of the gate within parenthesis, separated by commas. NOTE: the output must be listed first.

• e.g. " and AND_GATE1 (w1, A,B);" where w1 is the output and A & B are the inputs, listed in no particular order.

• • Comments are not part of the program but rather are intended to assist

the reader of the code to readily understand why the program is written as it is. When in doubt, add comments-a well documented program has much greater value than a poorly explained one.

• • Single line comments begin with // and continue to the end of the line.• Multiline comments begin with /* and end with */ • It should be noted that comment lines and endmodule do not end in

semicolons.

• • // Verilog model of circuit shown in fig. 3.35• • module Simple_Circuit (A,B,C,D,E);• output D,E;• input A,B,C;• wire w1;• • and G1 (w1,A,B); // Optional gate instance name• not G2 (E,C);• or G3 (D,w1,E);• endmodule• • Notes:• * endmodule does not end with a semicolon nor do the comments.• * This example shows keywords in bold as does your text. This is not necessary and is done merely to aid the reader in identifying the

keywords.• * The operations shown here are not done sequentially but rather simultaneously. Verilog is not a 'downflow' language like 'C' and others.

PROPAGATION DELAYS

• As you are aware, gates do not change their outputs at exactly the same time that their inputs change. This time delay is known as propagation delay and changes from gate to gate. The simulation software that we will be using, Modelsim, allows these delays to be considered when simulating modules.

• • In order for the simulator to do so, it needs to have a time reference

for the units of time that we will specify for each gate.• The keyword for doing this is `timescale followed by the duration of

each time unit and also the precision for rounding off the delays. e.g. `timescale 1ns/100ps means that each unit of time is defined as 1 nanosecond and the precision for rounding is 100 picoseconds.

• • NOTE: This keyword is a compiler directive and as such, the rules of

syntax are different than those previously discussed. It must begin with a tic ( `) and does not end with a semicolon.

• An example of the previous module which includes propagation delays follows:• • // Simple Circuit with propagation delays• • `timescale 1ns/100ps• module Simple_Circuit_with_Prop_Delays (A,B,C,D,E)• output D,E;• input A,B,C;• wire w1;• • and #(30) G1 (w1, A,B);• not #(10) G2 (E,C);• or #(20) G3 (D, w1,E);• endmodule• • The only differences in the code are the inclusion of the timescale keyword which is placed

before the beginning of the module and the amount of propagation delays of each gate.• e.g. the "#(30) placed ahead of the G1 description tells the simulator that the propagation

delay of G1 is 30 units of time. The timescale compiler keyword defined the individual units of time as 1 nanosecond so the propagation delay of our AND gate is 30 x 1ns=30ns