Lecture 7: Power. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 7: Power2 Outline Power and Energy Dynamic Power Static Power

Lecture 7: Power

CMOS VLSI DesignCMOS VLSI Design 4th Ed.7: Power 2

Outline Power and Energy Dynamic Power Static Power


Power and Energy Power is drawn from a voltage source attached to

the VDD pin(s) of a chip.

Instantaneous Power:

Energy:

Average Power:

( ) ( ) ( )P t I t V t

0

( )T

E P t dt

avg

0

1( )

TEP P t dt

T T


Power in Circuit Elements

VDD DD DDP t I t V

2

2RR R

V tP t I t R

R

0 0

212

0

C

C

V

C

dVE I t V t dt C V t dt

dt

C V t dV CV


Charging a Capacitor When the gate output rises

– Energy stored in capacitor is

– But energy drawn from the supply is

– Half the energy from VDD is dissipated in the pMOS transistor as heat, other half stored in capacitor

When the gate output falls– Energy in capacitor is dumped to GND– Dissipated as heat in the nMOS transistor

212C L DDE C V

0 0

2

0

DD

VDD DD L DD

V

L DD L DD

dVE I t V dt C V dt

dt

C V dV C V


Switching Waveforms

Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz


Switching Power

switching

0

0

sw

2sw

1( )

( )

T

DD DD

TDD

DD

DDDD

DD

P i t V dtT

Vi t dt

T

VTf CV

T

CV f

C

fswiDD(t)

VDD


Activity Factor Suppose the system clock frequency = f Let fsw = f, where = activity factor

– If the signal is a clock, = 1– If the signal switches once per cycle, = ½

Dynamic power:2

switching DDP CV f


Short Circuit Current When transistors switch, both nMOS and pMOS

networks may be momentarily ON at once Leads to a blip of “short circuit” current. < 10% of dynamic power if rise/fall times are

comparable for input and output We will generally ignore this component


Power Dissipation Sources

Ptotal = Pdynamic + Pstatic

Dynamic power: Pdynamic = Pswitching + Pshortcircuit

– Switching load capacitances– Short-circuit current

Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD

– Subthreshold leakage– Gate leakage– Junction leakage– Contention current

CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Power Dissipation Power dissipation breakdown in the Niagra 2

processor (Sun-8 core – 84W)

7: Power 11


Dynamic Power Example 1 billion transistor chip

– 50M logic transistors• Average width: 12 • Activity factor = 0.1

– 950M memory transistors• Average width: 4 • Activity factor = 0.02

– 1.0 V 65 nm process– C = 1 fF/m (gate) + 0.8 fF/m (diffusion)

Estimate dynamic power consumption @ 1 GHz. Neglect wire capacitance and short-circuit current.


Solution

6logic

6mem

2

dynamic logic mem

50 10 12 0.025 / 1.8 / 27 nF

950 10 4 0.025 / 1.8 / 171 nF

0.1 0.02 1.0 1.0 GHz 6.1 W

C m fF m

C m fF m

P C C


Dynamic Power Reduction

Try to minimize:

– Activity factor– Capacitance– Supply voltage– Frequency

2switching DDP CV f


Activity Factor Estimation

Let Pi = Prob(node i = 1)

– Pi = 1-Pi

i = Pi * Pi

Completely random data has P = 0.5 and = 0.25 Data is often not completely random

– e.g. upper bits of 64-bit words representing bank account balances are usually 0

Data propagating through ANDs and ORs has lower activity factor– Depends on design, but typically ≈ 0.1


Switching Probability


Example

A 4-input AND is built out of two levels of gates Estimate the activity factor at each node if the inputs

have P = 0.5


Example Compare the two cases below:

7: Power 18


Example

7: Power 19


Example

7: Power 20


Clock Gating

The best way to reduce the activity is to turn off the clock to registers in unused blocks– Saves clock activity ( = 1)– Eliminates all switching activity in the block– Requires determining if block will be used


Capacitance

Gate capacitance– Fewer stages of logic– Small gate sizes

Wire capacitance– Good floorplanning to keep communicating

blocks close to each other– Drive long wires with inverters or buffers rather

than complex gates


Voltage / Frequency Run each block at the lowest possible voltage and

frequency that meets performance requirements Voltage Domains

– Provide separate supplies to different blocks– Level converters required when crossing

from low to high VDD domains

Dynamic Voltage Scaling– Adjust VDD and f according to

workload


Voltage Domains

7: Power 24


Voltage Domains

7: Power 25


Voltage Domains The easiest approach is to associate each block in a

floorplan with a voltage You can also perform clustered voltage scaling

7: Power 26


Voltage Domains Dynamic voltage scaling

7: Power 27


Voltage Domains

7: Power 28


Short Circuit CurrentsShort Circuit Currents

Vin Vout

CL

Vdd

I VD

D (m

A)

0.15

0.10

0.05

Vin (V)5.04.03.02.01.00.0


How to keep Short-Circuit Currents Low?How to keep Short-Circuit Currents Low?

Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic, so ...


Minimizing Short-Circuit PowerMinimizing Short-Circuit Power

0 1 2 3 4 50

1

2

3

4

5

6

7

8

tsin

/tsout

Pno

rm

Vdd =1.5

Vdd =2.5

Vdd =3.3


Resonant Circuits Especially useful in clocking. IBM has demonstrated

resonant clocking for a practical processor.

7: Power 32


Static Power Static power is consumed even when chip is

quiescent.– Leakage draws power from nominally OFF

devices– Ratioed circuits burn power in fight between ON

transistors


Static Power Example Revisit power estimation for 1 billion transistor chip Estimate static power consumption

– Subthreshold leakage

• Normal Vt: 100 nA/m

• High Vt: 10 nA/m

• High Vt used in all memories and in 95% of logic gates

– Gate leakage 5 nA/m– Junction leakage negligible


Solution

t

t

t t

t t

6 6normal-V

6 6 6high-V

normal-V high-V

normal-V high-V

50 10 12 0.025 m / 0.05 0.75 10 m

50 10 12 0.95 950 10 4 0.025 m / 109.25 10 m

100 nA/ m+ 10 nA/ m / 2 584 mA

5 nA/ m / 2

sub

gate

W

W

I W W

I W W

275 mA

P 584 mA 275 mA 1.0 V 859 mWstatic


Subthreshold Leakage For Vds > 50 mV

Ioff = leakage at Vgs = 0, Vds = VDD

10gs ds DD sbV V V k V

Ssub offI I

Typical values in 65 nmIoff = 100 nA/m @ Vt = 0.3 VIoff = 10 nA/m @ Vt = 0.4 VIoff = 1 nA/m @ Vt = 0.5 V = 0.1k = 0.1S = 100 mV/decade


Stack Effect Series OFF transistors have less leakage

– Vx > 0, so N2 has negative Vgs

– Leakage through 2-stack reduces ~10x– Leakage through 3-stack reduces further

2 1

10 10x DD x DD xx DD V V V V k VV V

S Ssub off off

N N

I I I

1 2DD

x

VV

k

1

1 2

10 10

DDDD

kV

k V

S Ssub off offI I I


Threshold Effect

7: Power 38


Leakage Control Leakage and delay trade off

– Aim for low leakage in sleep and low delay in active mode

To reduce leakage:– Increase Vt: multiple Vt

• Use low Vt only in critical circuits– Increase Vs: stack effect

• Input vector control in sleep– Decrease Vb

• Reverse body bias in sleep• Or forward body bias in active mode


Gate Leakage

Extremely strong function of tox and Vgs

– Negligible for older processes– Approaches subthreshold leakage at 65 nm and

below in some processes An order of magnitude less for pMOS than nMOS Control leakage in the process using tox > 10.5 Å

– High-k gate dielectrics help

– Some processes provide multiple tox

• e.g. thicker oxide for 3.3 V I/O transistors Control leakage in circuits by limiting VDD


NAND3 Leakage Example

100 nm process

Ign = 6.3 nA Igp = 0

Ioffn = 5.63 nA Ioffp = 9.3 nA

Data from [Lee03]


Junction Leakage

From reverse-biased p-n junctions– Between diffusion and substrate or well

Ordinary diode leakage is negligible Band-to-band tunneling (BTBT) can be significant

– Especially in high-Vt transistors where other leakage is small

– Worst at Vdb = VDD

Gate-induced drain leakage (GIDL) exacerbates

– Worst for Vgd = -VDD (or more negative)


Power Gating Turn OFF power to blocks when they are idle to

save leakage– Use virtual VDD (VDDV)– Gate outputs to prevent

invalid logic levels to next block

Voltage drop across sleep transistor degrades performance during normal operation– Size the transistor wide enough to minimize

impact Switching wide sleep transistor costs dynamic power

– Only justified when circuit sleeps long enough


Power Gating When a block is gated, the state must either be saved or reset

upon power-up.

– Either use registers with a second VDD.

– Or save everything to memory. Power gating may be done externally with a disable input to a

voltage regulator or internally with high VT header or footer switches.

External power gating eliminates leakage altogether, but it takes a long time and significant energy.

The power transistor actually consists of many transistors in parallel which should be controlled individually to combat Ldi/dt and IR drops.

Also, best Ion/Ioff is obtained for specific L and W values.

7: Power 44


Multiple Thresholds Selective application of multiple threshold voltages

can maintain performance on critical paths with low-Vt transistors while reducing leakage on other paths with high-Vt transistors.

Using multiple thresholds adds to the cost of the process.

One can alternatively use non-minimum L transistors for non-critical paths, thus raising the threshold voltages via the short-channel effect.

For example, in Intel’s 65nm process, 10% longer transistors reduces Ion by 10%, but Ioff 3 times.

7: Power 45


Variable Thresholds Using body bias, one can dynamically adjust

threshold voltages. This is called variable threshold CMOS (VTCMOS). Use low-Vt devices and reverse body bias during

sleep. Alternatively, use high-Vt devices and forward body

bias during operation. Too much reverse body bias (e.g. < -1.2V) leads to

greater junction leakage due to BTBT. Too much forward body bias (e.g.>0.4V) leads to

large current through the body to source diodes.

7: Power 46


Variable Thresholds Below is an n-well process with body bias. Normally, triple well processes should be utilized.

7: Power 47


Input Vector Control Applying the pattern that consumes the least power

during sleeping could minimize the power in that block.

Be careful that applying this pattern itself causes power dissipation.

7: Power 48


Energy-Delay Optimization

What is the best choice for VDD and Vt in a certain technology and application?

What does “best” mean? Let us start with minimum energy. Energy corresponds to PDP. It occurs in the subthreshold region where VDD < Vt.

Von Neumann said that this could be found from thermodynamics and was kTln2.

Meindl found the minimum voltage that the inverter could operate at by equating the slope at the switching point to -1.

7: Power 49



He took n = 1 for subthreshold operation. The minimum voltage turns out to be

The energy stored on the gate capacitance of a MOSFET is

The minimum charge is q. Emin = kTln2 = 2.9 X 10-21 J.

0.5m 5V process, 1.5 X 10-13, 65nm 1V 3 X 10-16 J.

7: Power 50

€

Vmin = 2ln2kT

q

⎛

⎝ ⎜

⎞

⎠ ⎟= 36mV@300K

€

E =QVDD

2



However, this situation does not really minimize energy because the circuits run so slowly that the leakage energy dominates.

The true minimum energy is at a point where switching and leakage energies are balanced.

In subthreshold operation, current drops exponentially with VDD-Vt, switching energy improves quadratically with VDD.

Ignoring DIBL, gate and junction leakage, and short circuit power one can find the minimum energy point easily.

7: Power 51



7: Power 52


Minimum Energy The delay of N gates operating in subthreshold

region is given by

The energy consumed in one cycle is

7: Power 53

€

D =NkCgVDDIoff10VDD

€

E switching =CeffVDD2

E leak = IsubVDDD =WeffNkCg10−VDDVDD2

E total = E switching + E leak


Minimum Energy Note that this equation depends on switching

activity. Also, only inverters were used in the analysis. Other gates can also be considered. Temperature effects the behavior strongly. Even in this case, taking the derivative and equating

to zero yields messy equations. Contour plots are more informative.

7: Power 54


Minimum Energy

7: Power 55

= 1 = 0.1


Minimum Energy The minimum energy points are not practical

because the energy is decreased about 10 times, but the frequency is decreased 10000 – 100000 times.

A better alternative to take into account both energy and speed is energy delay product (EDP).

7: Power 56


Minimum EDP First, ignore leakage. Use the alpha-power law to include velocity

saturation. EDP is given by

Differentiating with respect to VDD and setting to zero

7: Power 57

€

EDP = kCeff

2 VDD3

VDD −Vt( )α

€

VDD−opt =3

3 −αVt


Minimum EDP is typically between 1 and 2. Hence, the optimum VDD is around 2Vt.

Differentiating with respect to Vt gives the optimum Vt to be zero.

This is because leakage was neglected. Leakage should also be introduced and the equation

should be solved again. The results are messy, but can be described in

terms of contour plots. The dashed lines represent speed normalized to the

minimum EDP point.7: Power 58


Minimum EDP

7: Power 59


Minimum Energy under a Delay Constraint

7: Power 60


Low Power Architectures

7: Power 61


Power Management Modes

7: Power 62


Power Management Modes

Intel Atom Processor– HFM: 2 GHz, 1 V, 2 W.– LFM: 600 MHz, 0.75 V.– Sleep modes: C1-C6

For a typical workload, the chip spends 80% - 90% of its time in C6 mode.

The average power drops to 220mW. Chips are usually designed for average power. Software designed to spend maximum power and

burn chips is called thermal virus.

7: Power 63


Pitfalls and Fallacies Oversizing gates Designing for speed regardless of power. Reporting power at a a given frequency rather than

energy per operation. Reporting PDP where actually EDP should be used. Failing to account for leakage.

7: Power 64

Documents

Lecture 7: Power. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 7: Power2 Outline Power and Energy Dynamic Power Static Power