Lecture 5: DC & Transient Response. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient Response2 Outline ï± Pass Transistors ï± DC Response ï±

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Text of Lecture 5: DC & Transient Response. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5: DC and Transient...

PowerPoint PresentationLecture 5:
CMOS VLSI Design
Outline
Transient Response
CMOS VLSI Design
Pass Transistors
What if source > 0?
Vg = VDD
Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded “1”
pMOS pass transistors pull no lower than Vtp
Transmission gates are needed to pass both 0 and 1
5: DC and Transient Response
CMOS VLSI Design
Pass Transistor Ckts
VDD
VSS
VDD
VDD
DC Response
Ex: Inverter
transistor size and current
Idsn = |Idsp|
5: DC and Transient Response
CMOS VLSI Design
Transistor Operation
For what Vin and Vout are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
CMOS VLSI Design
nMOS Operation
Vgsn = Vin
Vdsn = Vout
Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn
Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn
5: DC and Transient Response
CMOS VLSI Design
pMOS Operation
Vgsp > Vtp Vin > VDD + Vtp
Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp
Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp
5: DC and Transient Response
CMOS VLSI Design
I-V Characteristics
Make pMOS is wider than nMOS such that bn = bp
5: DC and Transient Response
Vgsn5
Vgsn4
Vgsn3
Vgsn2
Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
Current vs. Vout, Vin
CMOS VLSI Design
Load Line Analysis
Vout must be where |currents| are equal in
5: DC and Transient Response
CMOS VLSI Design
Load Line Analysis
Vin5
Vout
VDD
DC Transfer Curve
5: DC and Transient Response
CMOS VLSI Design
Operating Regions
Vout
VDD
Vin
Beta Ratio
If bp / bn 1, switching point will move from VDD/2
Called skewed gate
5: DC and Transient Response
CMOS VLSI Design
Noise Margins
How much noise can a gate input see before it does not recognize the input?
5: DC and Transient Response
CMOS VLSI Design
Logic Levels
unity gain point of DC transfer characteristic
5: DC and Transient Response
CMOS VLSI Design
Transient Response
Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations
Input is usually considered to be a step or ramp
From 0 to VDD or vice versa
5: DC and Transient Response
CMOS VLSI Design
Inverter Step Response
5: DC and Transient Response
CMOS VLSI Design
Delay Definitions
tpdf: falling propagation delay
tpd: average propagation delay
tf: fall time
5: DC and Transient Response
CMOS VLSI Design
Delay Definitions
tcdf: falling contamination delay
tcd: average contamination delay
CMOS VLSI Design
Simulated Inverter Delay
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write, may hide insight
5: DC and Transient Response
CMOS VLSI Design
Delay Estimation
We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask “What if?”
The step response usually looks like a 1st order RC response with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
5: DC and Transient Response
CMOS VLSI Design
Effective Resistance
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
Too inaccurate to predict current at any given time
But good enough to predict RC delay
5: DC and Transient Response
CMOS VLSI Design
RC Delay Model
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
CMOS VLSI Design
RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
Gradually decline to 1 fF/mm in nanometer techs.
Resistance
Improves with shorter channel lengths
Unit transistors
Or maybe 1 mm wide device
Doesn’t matter as long as you are consistent
5: DC and Transient Response
CMOS VLSI Design
Inverter Delay Estimate
d = 6RC
2C
2C
R
C
C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
Delay Model Comparison
CMOS VLSI Design
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
3
3
3
2
2
2
CMOS VLSI Design
3-input NAND Caps
Annotate the 3-input NAND gate with gate and diffusion capacitance.
5: DC and Transient Response
2
2
2
3
3
3
9C
2
2
2
3
3
3
3C
3C
5C
5C
5C
Elmore Delay
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
5: DC and Transient Response
CMOS VLSI Design
Example: 3-input NAND
Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates.
5: DC and Transient Response
9C
5hC
3C
3C
3
3
3
2
2
2
Y
n2
n1
Delay Components
CMOS VLSI Design
Contamination Delay
Ex: If all three inputs fall simultaneously
5: DC and Transient Response
9C
5hC
3C
3C
3
3
3
2
2
2
Y
n2
n1
Diffusion Capacitance
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too
5: DC and Transient Response
CMOS VLSI Design
Layout Comparison
V
out
V
DD
V
in
I
dsn
I
dsp
V
out
V
DD
V
in
V
in2
V
in2
I
dsn