Text of Lecture 3: Nonideal Transistor Theory. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 4: Nonideal...
PowerPoint PresentationLecture 3: Outline Ideal Transistor I-V Ideal vs. Simulated nMOS I-V Plot 65 nm IBM process, VDD = 1.0 V 4: Nonideal Transistor Theory ON and OFF Current Saturation Cutoff Electric Fields Effects Attracts carriers into channel Long channel: Qchannel Evert Long channel: v = mElat 4: Nonideal Transistor Theory Coffee Cart Analogy Vds is how long you have been up Your velocity = fatigue × mobility Vgs is a wind blowing you against the glass (SiO2) wall At high Vgs, you are buffeted against the wall Mobility degradation At high Vds, you scatter off freshmen, fall down, get up Velocity saturation 4: Nonideal Transistor Theory Mobility Degradation Collisions with oxide interface 4: Nonideal Transistor Theory Velocity Saturation Velocity reaches vsat Electrons: 107 cm/s Better model Example 1 Calculate the effective carrier mobilities of nMOS and pMOS transistors when fully ON. Assume Vgs = 1 V, Vt = 0.3 V and tox = 1.05 nm 4: Nonideal Transistor Theory Example 2 Find the critical voltage for nMOS and pMOS transistors that are fully ON, using the values obtained in example 1 and L = 50nm. (Hint Vc = EcL) 4: Nonideal Transistor Theory Vel Sat I-V Effects Velocity-saturated ON current increases with VDD Real transistors are partially velocity saturated Approximate with a-power law model Ids VDDa 4: Nonideal Transistor Theory a-Power Model Channel Length Modulation Region between n and p with no carriers Width of depletion Ld region grows with reverse bias Leff = L – Ld Ids increases with Vds Chan Length Mod I-V not feature size 4: Nonideal Transistor Theory Threshold Voltage Effects Vt is Vgs for which the channel starts to invert Ideal models assumed Vt is constant Really depends (weakly) on almost everything else: Body voltage: Body Effect 4: Nonideal Transistor Theory Body Effect Vsb affects the charge required to invert the channel Increasing Vs or decreasing Vb increases Vt fs = surface potential at threshold Depends on doping level NA And intrinsic carrier concentration ni g = body effect coefficient 4: Nonideal Transistor Theory Body Effect Cont. 4: Nonideal Transistor Theory DIBL Electric field from drain affects channel More pronounced in small transistors where the drain is closer to the channel Drain-Induced Barrier Lowering High drain voltage causes current to increase. 4: Nonideal Transistor Theory Short Channel Effect In small transistors, source/drain depletion regions extend into the channel Impacts the amount of charge required to invert the channel And thus makes Vt a function of channel length Short channel effect: Vt increases with L Some processes exhibit a reverse short channel effect in which Vt decreases with L 4: Nonideal Transistor Theory Leakage Simulated results What differs? 4: Nonideal Transistor Theory Leakage Sources Subthreshold conduction Dominant source in contemporary transistors Gate leakage Junction leakage 4: Nonideal Transistor Theory Subthreshold Leakage n is process dependent S ≈ 100 mV/decade @ room temperature 4: Nonideal Transistor Theory Gate Leakage Exponentially sensitive to tox and VDD A and B are tech constants Greater for electrons Negligible for older processes (tox > 20 Å) Critically important at 65 nm and below (tox ≈ 10.5 Å) From [Song01] Junction Leakage Ordinary diode leakage Band-to-band tunneling (BTBT) Diode Leakage At any significant negative diode voltage, ID = -Is Is depends on doping levels And area and perimeter of diffusion regions Typically < 1 fA/mm2 (negligible) 4: Nonideal Transistor Theory Band-to-Band Tunneling Especially sidewall between drain & channel when halo doping is used to increase Vt Increases junction leakage to significant levels Xj: sidewall junction depth Gate-Induced Drain Leakage Occurs at overlap between gate and drain Most pronounced when drain is at VDD, gate is at a negative voltage Thwarts efforts to reduce subthreshold leakage using a negative gate voltage 4: Nonideal Transistor Theory Temperature Sensitivity Increasing temperature Reduces mobility Reduces Vt So What? They still behave like switches. But these effects matter for… Supply voltage choice Parameter Variation Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values Fast (F) Leff: short Vt: low tox: thin for nMOS and pMOS 4: Nonideal Transistor Theory Environmental Variation Fast: Process Corners Process corners describe worst case variations If a design works in all corners, it will probably work for any variation. Describe corner with four letters (T, F, S) nMOS speed pMOS speed Important Corners Purpose nMOS pMOS VDD Temp Example 3 Consider an nMOS transistor manufactured in 65nm process, with nominal threshold voltage equal to 0.3 V and doping levels of 8x10^17 cm^(-3). The substrate is connected to ground with a contact. What will be the change in the treshold voltage at room temperature if the sourse is at 0.6V instead of 0V? (Assume tox = 1.05 nm, q=1.6x10^(-19) Cb, vT = kT/q = 26mV, ni = 1.45x10^10 cm^(-3), εox = 3.9x8.85x10^(-14) F/cm, εSi = 11.7x8.85x10^(-14) F/cm) 4: Nonideal Transistor Theory Example 4 An nMOS transistor has a threshold voltage of 0.4V and Vdd = 1.2V. A designer considers reducing the threshold voltage by 100 mV in order to increase transistor speed (i) By how much would the saturation current increase (for Vgs=Vds=Vdd) if the transistors were ideal? (ii) By how much would the subthreshold leakage current increase in room temperature for Vgs=0; Assume n=1.4 (iii) By how much would the subthreshold leakage current increase at 120°C? Assume that Vt is constant. k=1.380 6504(24)×10−23 J/K 4: Nonideal Transistor Theory Example 5 Find the subthreshold leakage current of an inverter at room temperature if the input A=0. Let βn=2βp = 1mA/V^2., n=1.4, and ABS(Vt)=0.4V. Assume the body effect and DIBL coefficients are zero. 4: Nonideal Transistor Theory p substrate quadratically with V 0 0 e1e gstdssb ds TT VVVkV V nvv dsds II g h
