Pass transistor adiabatic logic for low power VLSI design

PASS TRANSISTOR ADIABATIC LOGIC FOR

LOW POWER VLSI DESIGN

A DISSERTATION SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT THE AWARD OF DEGREE OF

BACHELOR OF TECHNOLOGY in

ELECTRONICS ENGINEERING

Under the guidance of

Supervisor: Prof. S. K. Balasubramanian

Co-supervisor: Mr. Chandan Rai

Submitted by

Akanksha Trigun Animesh Jain

Siddharth Agarwal

DEPARTMENT OF ELECTRONICS ENGINEERING

INSTITUTE OF TECHNOLOGY

BANARAS HINDU UNIVERSITY

VARANASI-221005

Pass transistor adiabatic logic for low power VLSI design 2011

3

Gram : Electronics Engineering Phone No : 2307014, 2307011 (off)

2307010 (HOD) Fax : 91-0542-2366758 Email : [email protected]

Date ………………………………

Institute of Technology

Banaras Hindu University, Varanasi



Ref.No.IT/EcE/ ……………

CERTIFICATE

and Mr. Siddharth Agarwal (Roll No:07000506), to the Department of Electronics Engineering,

This is to certify that the dissertation entitled “Pass Transistor Adiabatic Logic for low power VLSI design”

submitted by Ms. Akanksha Trigun (Roll No:07000536), Mr. Animesh Jain (Roll No:07000511)

Institute of Technology, Banaras Hindu University, Varanasi, in partial fulfilment of the requirements

for the award of the degree "BACHELOR OF TECHNOLOGY" in Electronics Engineering is a

bona fide record of the work carried out by them under our supervision and guidance.

(Prof. S.K. Balasubramanian)

Supervisor

Department of Electronics Engineering

(Prof. S. P. Singh)

HEAD OF DEPARTMENT


Co-supervisor

(Mr. Chandan Rai)


mailto:[email protected]


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BANARAS HINDU UNIVERSITY

VARANASI-221005, (INDIA)

CANDIDATE’S DECLARATION

We declare that the dissertation for B.Tech entitled “PASS TRANSISTOR

ADIABATIC LOGIC FOR LOW POWER VLSI DESIGN” is our own work

conducted under the guidance of Prof. S.K. Balasubramanian and Mr.

Chandan Rai. We further declare that to the best of our knowledge, the

dissertation for B.Tech does not contain any part of the work, which has been

submitted for the award of any degree either in this University or in other

University/Deemed University without proper citation.

Akanksha Trigun

(Roll No. 07000536

Enrolment No. 296277)

Animesh Jain

(Roll No. 07000511


Siddharth Agarwal

(Roll No. 07000506



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ACKNOWLEDGEMENT

The completion of the work for this thesis represents the opportunity to

remember numerous individuals who have influenced our attitude towards

undergraduate studies. We would like to acknowledge our debt to our

professors, family and friends.

First and foremost, we would like to thank our supervisor Prof. S.K.

Balasubramanian, Institute of Technology, Banaras Hindu University,Varanasi

for endless hours of help, suggestions, ideas,motivation and advice during the

development of the thesis. We would like to thank him for his focus and talks to

keep us on track. We are indebted to him for giving us an opportunity to work

under him and for his wholehearted support and suggestions.

Our gratitude to him for providing effective management, necessary facilities

and valuable suggestions responsible for the success of this work. Thanks are

also due to very helping and insightful Mr. Chandan Rai, Department of

Electronics Engineering, IT BHU, Varanasi for his timely help, suggestions and

enthusiasm. We would also like to thank all the faculty members, VLSI CAD

Lab members and the librarians for their kind co-operation and encouragement

during the course of the work.

VARANASI Akanksha Trigun

MAY 2011 Animesh Jain

Siddharth Agarwal


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ABSTRACT

The main objective of this thesis is to provide new lower power solutions for Very Large

Scale Integration (VLSI) designers. Especially, this work focuses on the reduction of the

power dissipation, which shows an ever-increasing growth with the scaling down of the

technologies. Various techniques, at the different levels of the design process have been

implemented to reduce the power dissipation at the circuit, architectural and system level.

Furthermore, the number of gates per chip area is constantly increasing, while the gate

switching energy does not increase at the same rate, so the power dissipation rises and heat

removal becomes more difficult and expensive. Then, to limit the power dissipation,

alternative solutions at each level of abstraction are proposed.

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in

the design of personal information systems and large computers. In this thesis work, a new

CMOS logic family called PASS TRANSISTOR ADIABATIC LOGIC, based on the

adiabatic switching principle is presented. The term ADIABATIC comes from the Greek word

that is used to describe thermodynamic processes that has exchange of no energy with the

environment and therefore, no energy loss in the form of dissipated heat. The adiabatic logic

structure dramatically reduces the power dissipation. The adiabatic switching technique can

achieve very low power dissipation, but at the expense of circuit complexity. Adiabatic logic

offers a way to reuse the energy stored in the load capacitors rather than the traditional way

of discharging the load capacitors to the ground and wasting this energy.

This thesis work demonstrates the low power design for VLSI.


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Chapter

1. INTRODUCTION

1.1 MOTIVATION

In the past few decades, the electronics industry has been experiencing an unprecedented

spurt in growth, thanks to the use of integrated circuits in computing, telecommunications

and consumer electronics. We have come a long way from the single transistor era in

1958 to the present day ULSI (Ultra Large Scale Integration) systems with more than 50

million transistors in a single chip [1].

The ever-growing number of transistors integrated on a chip and the increasing transistors

switching speed in recent decades has enabled great performance improvement in

computer systems by several orders of magnitude. Unfortunately, such phenomenal

performance improvements have been accompanied by an increase in power and energy

dissipation of the systems. Higher power and energy dissipation in high performance

systems require more expensive packaging and cooling technologies, increase cost, and

decrease system reliability. Nonetheless, the level of on-chip integration and clock

frequency will continue to grow with increasing performance demands, and the power

and energy dissipation of high-performance systems will be a critical design constraint.

For example, high-end microprocessors in 2010 are predicted to employ billions of

transistors at clock rates over 30GHz to achieve TIPS (Tera Instructions per seconds)

performance [1]. With this rate, high-end microprocessor’s power dissipation is projected

to reach thousands of Watts. This thesis investigates one of the major sources of the


8

power/energy dissipation and proposes and evaluates the techniques to reduce the

dissipation.

Digital CMOS integrated circuits have been the driving force behind VLSI for high

performance computing and other applications, related to science and technology. The

demand for digital CMOS integrated circuits will continue to increase in the near future,

due to its important salient features like low power, reliable performance and

improvements in the processing technology.

1.2 Need of Low Power VLSI Design

Power dissipation is defined as the rate of energy delivered from source to system/device.

Recently, Power dissipation is becoming an important constraint in a design. Several

reasons underline the emerging of this issue. Among them some are presented here:

The need for battery powered systems such as laptop/notebook computers,

electronic organizers, etc. requires that they have extended battery life. Many

portable applications use the rechargeable Nickel Cadmium (NiCd) batteries.

Although the battery industry has been making efforts to develop batteries

with higher energy capacity than that of NiCd, a strident increase does not

seem imminent. The expected improvement of the energy density is 40% by

the turn of century. Even with the advanced battery technologies, such as

Nickel-Metal Hydride (Ni-MH) which provide energy density characteristics

(30 Watt-hour/pound), the lifetime of battery is still low. Since battery

technology has offered a limited improvement, low power design techniques

are essential for portable devices [1].

Low power is not only needed for portable applications but also to reduce the

power of high performance systems. With large integration density and

improved speed of operation, systems with high clock frequencies are

emerging. These systems are using high speed processors and associated

circuits which increase the power consumption. The cost associated with


9

cooling, packaging and fans required by these systems to remove the heat

generated because of power consumption is increasing significantly.

As shown in Figure 1.1, the power consumption of the lead Intel

microprocessors has been increasing significantly for almost every generation

over the past 30 years. The frequency changes during this era from several

MHz to 3 GHz. So, this figure shows that, at higher frequencies, the power

dissipation is too excessive.

Figure - 1.1 Maximum power consumption of lead Intel Microprocessor [2]

Ultra Large Scale Integration (ULSI) reliability is yet another concern which

points to the need of low power design. There is a close correlation between

the peak power dissipation of digital circuits and the reliability problems such

as electro migration and hot-carrier induced device degradation.


10

Consequently, the reduction of power consumption is also crucial for

reliability enhancement.

The methodologies which are used to achieve low power consumption in digital systems

span a wide range, from device/process level to algorithm level. Device characteristics,

device geometries and interconnect properties are significant factors in lowering power

consumption. Circuit level and Architecture level design measures are used to achieve low

power consumption.

Finally, the power consumed by the system can be reduced by a proper selection of data

processing algorithms, especially to minimize the number of switching events for a given

task.

1.3 Sources of Power Consumption in CMOS ICs

Power consumption is a primary limitation to the further advancement of semiconductor

technologies. Identifying the sources of power consumption is critical for developing

power reduction techniques at the fabrication technology, circuit, and architecture levels.

There are mainly three sources of power consumption in CMOS circuits.

Dynamic Power Consumption(Pdynamic )

Leakage Power Consumption(Pleakage )

Short-circuit Power Consumption(Pshort-circuit )

So the total power consumption of a CMOS circuit is

Ptotal = Pdynamic + Pleakage + Pshort-circuit

1.3.1 Dynamic Power Consumption

The dominant component of power consumption in a typical CMOS circuit is the

dynamic switching power [2]. The dynamic switching power is dissipated while charging

or discharging the parasitic capacitances during the voltage transitions of the nodes within


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a CMOS circuit. The dynamic switching power is independent of the type of switching

gate and the shape of the input waveform (input rise and fall times). The dynamic

switching power is dependant only on the supply voltage, the switching frequency, the

initial and final voltages, and the equivalent capacitance of a switching node [3]. Since

the switching power is independent of the type of switching gate, a block diagram

representation of a generic CMOS gate (as shown in Figure 1.2) is used in this section to

explain dynamic switching power dissipation in CMOS circuits.

Input

CL

Figure - 1.2 A CMOS gate driving an output capacitor

In figure 1.2, the output capacitor consists of the drain-to-body junction capacitances

of the driver gate, the total interconnect capacitance, and the

Input gate oxide capacitance of the transistors of the driven gate. The total capacitive load

at the output is given as:

CL = Cdrain + Cinterconnect + Cinput

The average power dissipation of the CMOS logic gate driven by a period input

voltage waveform with zero rise and fall time can be calculated from the energy required

to charge up the output node to VDD and charge down the total output capacitance to

ground level and is given by

Pavg = [ ] (1)

Pull Up

Network

Pull Down

Network


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Evaluating this integral yields the well-known expression for the average dynamic

power consumption in CMOS logic circuits,

Pavg = CL (2)

= CL (3)

where is the clock frequency.

In a CMOS IC, all the internal nodes do not necessarily change their states at each clock. In a

synchronous CMOS IC, if statistical data are available for the average number of transitions

experienced by a node during the execution of a certain task, an average activity factor can be

introduced into the power and energy expressions. The average power consumed for

switching a node ‘i’ in a CMOS circuit is

Pi = αiCL (4)

where Pi is the average dynamic switching power dissipation of the gate driving the ith node

and αi is the probability that a state changing voltage transition will occur at the ith node

within one clock cycle.

In general terms, internal node transitions can be partial i.e. the node voltage swing

may be Vi which is much smaller than the full voltage swing . Thus, the generalised

expression for the average switching power dissipation can be written as [4]:

Pavg = ( ) (5)

Where Ci represents the parasitic capacitance associated with each node in the circuit

(including the output node).

1.3.2 Leakage Power Consumption

Dynamic switching power consumption has typically been the dominant source of power

consumption in CMOS ICs. Recently, however, leakage power has become a significant

portion of the total power consumption in high complexity CMOS ICs, as illustrated in

Figure 1.3. Ideally, a MOS switch has infinite input impedance. Similarly, an ideal cut-

off transistor has infinite drain-to-source resistance. However, in reality, an active


13

transistor has finite input impedance and a cut-off transistor has a finite channel

resistance, producing gate oxide and sub threshold leakage current, respectively. Due to

the aggressive scaling of the threshold voltages and the thickness of the gate dielectric

layer in order to enhance device speed, modern MOSFETs no longer resemble, even

remotely, an ideal switch. As illustrated in Figure 1.3, sub threshold and gate oxide

currents will become the dominant source of power consumption in future.

Figure - 1.3 Increasing contributions of leakage currents to the total power consumption

of the lead Intel microprocessors [2]

So, the leakage currents are dominated by weal inversion (sub threshold conduction) and

reverse biased p-n junction diode currents in long channel devices [1]. In deep sub

micrometer ICs, other leakage mechanisms such as drain-induced barrier lowering (DIBL)

and gate oxide tunnelling are also important [2].

Reverse biased P-N Junction Leakage Current

The reverse diode leakage occurs when the p-n junction between the drain and bulk of the

transistor is reversing biased. The reverse-biased drain junction then conducts a reverse

saturation current which is eventually drawn from the power supply.


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The magnitude of the reverse leakage current of a p-n junction is given by the

following expression [4]:

( - 1) (6)

Where Vbias is the reverse bias voltage across the junction is the reverse saturation current

density and A is the junction area, k is Boltzmann’s constant and T is absolute temperature in

Kelvin. Note that the reverse leakage occurs even during the stand-by operation when there is

no switching activity. Hence, the power dissipation can be significant in a large chip

containing several million transistors.

Sub threshold Leakage Current

A MOSFET operates in the weak inversion (sub threshold) region when the magnitude of the

gate-to-source voltage is less than the magnitude of the threshold voltage [1], [5]. In the weak

inversion mode, current conduction between the source and the drain (the sub threshold

leakage current) is primarily due to diffusion of the carriers [4]. Note that the sub threshold

leakage current also occurs when there is no switching activity in the circuit, and this

component must be carefully considered for estimating the total power dissipation in the

stand-by operation mode.

The sub threshold leakage current in a short-channel MOSFET can be characterized

by the following expression [4]:

Isub threshold = (7)

where is the carrier mobility, W is the transistor width, Cox is the oxide capacitance per

unit area, VT is the thermal voltage, VGS is the gate-to-source voltage, Vt is the threshold

voltage, n is the sub threshold swing coefficient and VDS is the drain-to-source voltage.

The sub threshold leakage current is exponentially dependant on the junction

temperature and the gate-to-source, drain-to-source, and threshold voltages. One relatively

simple measure to limit the sub threshold current component is to avoid very low threshold

voltages, so that the VGS of the NMOS transistor remains safely below Vtn when the input

logic is zero, and the |VGS| of the PMOS transistor remains safely below Vtp when the input

logic is one.


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1.3.3 Short-Circuit Power Consumption

In static CMOS circuits, there is a time period during the transition of the input signals

when both the pull-up and pull-down network transistors are simultaneously on, thereby

forming a DC current path between the power supply and ground. The DC current

conducted by a CMOS circuit during an input signal transient (due to non-zero rise and

fall times of the input signals) is called the short-circuit current [4]. The short-circuit

current (Ishort-circuit) is temporarily observed during the input signal transition, Vtn < Vin

<VDD + Vtp as illustrated in figure 1.4.

VDD

PMOS

Vout

Cload

NMOS

Figure – 1.5 Short circuit current during transition

Short-circuit current is a function of the output load and the rise and fall times of the

input and output signals. The short-circuit current can be significantly when the rise and

fall times of the input signals are significantly larger than the output rise and fall times as

the short-circuit current path will exist for a long period of time.

The time-averaged short circuit current drawn from the power supply is given by [4]:

(8)

where = input rise and fall time.

The short-circuit power typically contributes to less than 10% of the total power

consumed in a CMOS circuit provided that the input slew rate is higher than the output slew

rate [4]. The short-circuit power consumption can dominate the total power consumption of a


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CMOS circuit if the output is lightly loaded. Similarly, the short-circuit power consumption

can be as high as the dynamic switching power consumption if the input signal rise and fall

times are unusually long.

In addition to the three major sources of power consumption in CMOS digital

integrated circuits, some chips may also contain components or circuits which actually

consume static power. One example is the pseudo-nmos logic circuit. The presence of such

circuit blocks should also be taken in to account when estimating the overall power

dissipation of a complex system.

1.4 Low Power VLSI Design Methodologies

In order to optimize the power dissipation of digital systems, low-power methodology

should be applied throughout the design process from system level to process level, while

realizing that performance is still essential. Thus the parts or blocks consuming an

important fraction of the power are properly optimized for power saving. Figure 1.5

shows the different design levels of an integrated system. The process technology is under

the control of the device/process designer [1].

1.4.1 Power Reduction Through Process Technology

One way to reduce the power is to reduce the supply voltage but it increases the delay

significantly, particularly when VDD approaches the threshold voltage. To overcome this

problem the device should be scaled properly. The advantages of scaling for low-power

operation are the following:

1) Improved devices’ characteristics for low power operation. This is due to the

improvement of their current drive capabilities;

2) Reduced capacitances through small geometries and junction capacitances;

3) Improved interconnect technology;

4) Higher density of integration. It was shown that the integration of a whole

system in to a single chip provides orders of magnitude power saving [6].


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1.4.2 Power Reduction Through Circuit/Logic Design

To minimize the power at circuit/logic level, many techniques can be used such as [1]:

1) Use of more static style over dynamic style;

Figure - 1.5 Power reduction design space

2) Reducing the switching activity;

3) Optimizing the clock and bus loading;

4) Use of multi-Vt circuits;

5) Use of custom design which may improve the power; however the design cost

will increase;

6) Reducing VDD in non-critical paths;

7) Smaller transistor sizing.

1.4.3 Power Reduction Through Architectural Design

At the architectural level, several approaches can be applied to the design [1]:

1) Power management techniques when unused blocks are shutdown;

SYSTEM

ALGORITHM

ARCHITECTURE

LOGIC/CIRCUIT

DEVICE/PROCESS


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2) Low power architectures based on parallelism, pipelining, etc;

3) Reduction of the number of the global buses;

4) Minimization of instruction set for simple decoding and execution;

1.4.4 Power Reduction Through Algorithm Selection

Among the techniques to minimize the power at the algorithm level we cite[1]:

1) Switching activity;

2) Minimizing the number of operations and hence the number of hardware

resources;

3) Data coding for minimum switching activity.

1.4.5 Power Reduction in System

The system level is also important to the whole process of power optimization. Some

techniques are [1]:

1) Utilizing low system clocks. Higher frequencies are generated with on-chip

phase locked loop;

2) Using high level of integration. Integrated off-chip memories and other ICs

such as digital and analog peripherals.

1.5 Problem Definition

Among various approaches for low-power VLSI design, we have focussed on the power

through circuit/logic design approach. We used clocked logic for low power applications

called “Pass Transistor Adiabatic Logic (PAL)” to achieve lower power consumption.

In conventional level-restoring CMOS logic circuits with rail-to-rail output voltage

swing, each switching event causes an energy transfer from the power supply to the

output node or from the output node to the ground. During a 0-to-VDD transition of the

output, the total output charge Q = Cload VDD is drawn from the power supply at a constant

voltage. Thus, an energy of Esupply= Cload VDD2

is drawn from the power supply during


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this transition. Charging the output node capacitance to the voltage VDD means that at the

end of the transition, the amount of stored energy in the output node is Estored= Cload VDD2

/ 2. Thus, half of the injected energy from the power supply is dissipated in the PMOS

network while only one half is delivered to the output node. During a subsequent VDD – to

– 0 transition of the output node, no charge is drawn from the power supply and the

energy stored in the load capacitance is dissipated in the NMOS network.

The adiabatic logic structure dramatically reduces the power dissipation. Adiabatic logic

offers a way to reuse the energy stored in the load capacitors rather than the traditional

way of discharging the load capacitors to the ground and wasting this energy.

1.6 Organization of the Thesis

The primary goal of this thesis is to demonstrate a circuit level design approach, for use in

designs which demand extreme low power dissipation.

This thesis is organized as follows:

CHAPTER 1: INTRODUCTION This chapter introduces power consumption issues in

the area of VLSI. This chapter also summarizes the need of low power design in the

today’s era of scaling down of technologies and nanotechnology. Finally, this thesis

chapter explains organisation of the thesis.

CHAPTER 2: BASIC OF ADIABATIC LOGIC. This chapter explains the principle of

adiabatic switching that emerges as a new approach to low power VLSI design, followed

up by selection of power supply for Adiabatic logic.

CHAPTER 3: DESIGN OF TWO PHASE SINUSOIDAL POWER CLOCK This

chapter focuses on the operational and structural details of the two phase sinusoidal

power supply and clocked transmission gate adiabatic logic.

CHAPTER 4: DESIGN AND ANALYSIS OF LOW POWER STRUCTURES: This

chapter describes the technique of Pass Transistor Adiabatic Logic (PAL) which has been


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used as the technique for reduction in power consumption in the thesis. Further, this

chapter gives the details of all the cell structures made using PAL and the results of

reduction in power dissipation.

CHAPTER 5: DESIGN AND IMPLIMENTATION OF 8 BIT CARRY

LOOK AHEAD ADDER USING THE PASS TRANSISTOR ADIABATIC

LOGIC AND ANALYSIS OF POWER DISSIPATION PATTERN OF THE

CIRCUIT: this chater shows the implementation and testing of the PAL technique on an

8 bit carry look ahead adder circuit and on a onventional CMOS circuit and comparing

the results.


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CHAPTER

2

BASIC OF ADIABATIC LOGIC

The popularity of complementary MOS technology can be mainly attributed to inherently

lower power dissipation and high levels of integration. However, the current trend towards

ultra low-power has made researchers search for techniques to recover/recycle energy from

the circuits. In the early days, researchers largely focused on the possibility of having

physical machines that consume almost zero energy while computing and tried to find the

lower bound of energy consumption.

In conventional level-restoring CMOS logic circuits with rail-to-rail output voltage swing,

each switching event causes an energy transfer from the power supply to the output node or

from the output node to the ground. During a 0-to-VDD transition of the output, the total

output charge Q=CloadVDD is drawn from the power supply at a constant voltage. Thus, an

energy of Esupply= CloadVDD2 is drawn from the supply during this transition. Charging the

output node capacitance to the voltage level VDD means at the end of the transition, the

amount of stored energy in the output node Estored = CloadVDD2/2. Thus, half of the injected

energy from the power supply is dissipated in the PMOS network while only one half is

delivered to the output node. During a subsequent VDD-to-0 transition of the output node, no

charge is drawn from the power supply and energy stored in the load capacitance is dissipated

in the NMOS network [8].

To reduce the dissipation, the circuit designer can minimize the switching events, decrease

the node capacitance, reduce the voltage swing, or apply a combination of these methods. Yet

in all these cases, the energy drawn from the power supply is used only once being dissipated.


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To increase the energy efficiency of the logic circuits, other measures can be introduced for

recycling the energy drawn from the power supply. A novel class of logic circuits called

adiabatic logic offers the possibility of further reducing energy dissipation during the

switching events, and the possibility of recycling, reusing, some of the energy drawn from the

supply. To accomplish this goal, the circuit topology and the operating principles have to be

modified, sometimes drastically. The amount of energy recycling achievable using adiabatic

techniques is also determined by the fabrication technology, switching speed, and the voltage

swing [7,8].

2.1 Origin of ADIABATIC Logic

The word ADIABATIC comes from the Greek word that is used to describe thermodynamic

processes that exchange of no energy with the environment and therefore, no energy loss in

the form of dissipated heat.

In principle, a computing engine need not dissipate any energy; the transfer of energy through

a dissipative medium dissipated arbitrarily small amounts of energy if that transfer is made

sufficiently slowly.

In CMOS based circuits, the node voltages represent one of two logical values. During

operation, the logical values of these nodes, and their voltage levels, repeatedly toggle

between the two valid levels. Given the capacitances of these nodes, we can view performing

computation using CMOS circuits as moving charge from one node to another. In other

words, to perform useful work in CMOS, we are continuously forced to place and remove

charge from various nodes in the circuit. Charge transfer between nodes of different

potentials is similar to shuttling heat between two heat baths at different temperatures.

As an example, it is possible to shuttle energy between two heat baths at different

temperatures while losing arbitrarily small amounts of energy. This is done by inserting an

infinite number of heat baths between the two original ones such that the temperature

difference between any two adjacent baths becomes infinitesimally small. Shuttling heat


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packets reversibly between the baths at the two extremes following this gradual temperature

staircase results in arbitrarily small energy loss.

In general, if lossless reversibility is to be achieved, a process must be carried out at a slow

enough rate so that in effect, the system is always in equilibrium.

In this light, the reversible process may be regarded as a series of quasi-static changes along a

sequence of neighbouring equilibrium states.

2.1.1 Quasi-static Switching

Currently the power consumption of CMOS circuits drops linearly with lower operating

frequency. This means that the energy consumed per cycle is constant since the cycle is

inversely proportional to frequency. Typically in CMOS, each cycle contains some amount of

computational work and on the average the same amount of charge shuttling. This suggests

that in conventional CMOS, the energy consumed per charge movement is always constant.

This is analogous to the worst case scenario in our thermal example in which there were no

additional intermediate thermal baths and the transfers between the two baths were done in

one step. The reason for the high dynamic dissipation of conventional CMOS is the fact that

charge transfer within them happens abruptly, i.e., not quasi-statically. The time constant

associated with charging a gate through a similar transistor is RC, where R is the ON

resistance of the device and its input capacitance. However, the cycle time can be, and

usually is, much larger than RC. An obvious conclusion is that energy consumption can be

reduced by spreading the transitions over the whole cycle thus making them closer to quasi-

static processes rather than “squeezing” them all inside one RC.

To asymptotically reduce the energy dissipation in CMOS, all of the charge movements

through the circuits proceed quasi-statically. To achieve this quasi-static operation, one has to

guarantee absolute adherence to two conditions:

1) The first is to guarantee that charge flow between any two nodes in the circuit

occurs in a gradual and externally controlled manner. This means that we


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forbid any device in our circuit from turning on while there is a potential

difference across it. It also means that once the device is turned on, the

movement of charge through it must be done in a gradual and controlled

manner so as to prevent a potential difference from developing.

2) The second is to guarantee that the path followed by the charge does not

contain any parts that violate quasi-static behaviour. This means that the

circuit should not contain any non-linear dissipative elements.

In order to achieve gradual changes in the circuit, we have to replace constant power supply

(VDD) by linearly increasing voltage source [8].

2.2 PRINCIPLE OF ADIABATIC SWITCHING

The word ADIABATIC comes from the Greek word that is used to describe thermodynamic

processes that exchange of no energy with the environment and therefore, no energy loss in

the form of dissipated heat. In real-life computing, such ideal process cannot be achieved

because of presence of dissipative elements like resistance in a circuit. However, one can

achieve very low energy engine dissipation by slowing down the speed of operation and only

switching transistors under certain conditions. The signal energies stored in the circuit

capacitances are recycled instead of being dissipated as heat. The adiabatic logic is also

known as ENERGY RECOVERY CMOS [3].

It should be noted that the fully adiabatic operation of the circuit is an ideal condition which

may be approached asymptotically as the switching process is slowed down. In most practical

cases, the energy dissipation associated with a charge transfer event is usually composed of

an adiabatic component and a non-adiabatic component. Therefore, reducing all the energy

loss to zero may not possible, regardless of the switching speed. With the adiabatic switching

approach, the circuit energies are conserved rather than dissipated as heat. Depending on the

application and the system requirements, this approach can sometimes be used to reduce the

power dissipation of the digital systems.


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VDD

PMOS Q

Vin

Cload

NMOS

Figure - 2.1.a

VDD

Q

R

Cload

R

Figure - 2.1.b

Figure - 2.1.c


26

Fig 2.1 Circuits Explaining Adiabatic Switching

Here, the load capacitance is charged by a constant-current source (instead of the constant-

voltage source as in the conventional CMOS circuits).

Here R is the resistance of the PMOS network. A constant charging current corresponds to a

linear voltage ramp. Assume, the capacitor voltage VC is zero initially [12].

Therefore, the voltage across the switch = IR

P(t) in the switch = I2

R

Therefore Energy during charge = (I2

R)T

E=( I2

R)T = (CV/T)2 RT = C

2V

2R/T

Hence, E = Ediss = (CV/T)2 RT

where, the various terms are described as follows:

E- energy dissipated during charging,

Q- charge being transferred to the load,

C- value of the load capacitance,

R- resistance of the MOS switch turned on,

V- final value of the voltage at the load,

T- time spent for charging.

Now, a number of observations can be made as follows:

a. The dissipated energy is smaller than for the conventional case, if the

charging time T is larger than 2RC, i.e., the dissipated energy can be made

arbitrarily small by increasing the charging time,

b. Also, the dissipated energy is proportional to R, as opposed to the

conventional case, where the dissipation depends on the capacitance and the

voltage swing. Thus, reducing the on-resistance of the PMOS network will

reduce the energy dissipation [9].


27

2.2.1 Simple Example showing how energy dissipation can be minimized

VDD

Y

X

C

Figure - 2.2.a

:

X=0 Y:

Y

Figure - 2.2.b

Figure - 2.2 Logic of adiabatic power minimization

In CMOS circuits, charges are fed from the power supply, steered through MOSFET devices,

and then dumped into the ground terminal. To change a node’s voltage with associated

capacitance C, as shown in figure 2.1.a, VDDQ (= CVDD2) of energy is extracted from the VDD

terminal. Half of the energy 1/2CVDD2 is stored in capacitance temporarily, and the other half

is dissipated in the path. Although energy is dissipated in the channel resistance and wire

resistance, the amount of dissipated energy 1/2VDDQ, only depends on the voltage and the

amount of charge which flows through, and is independent of the resistance. Later, when this

node is converted to the ground, the stored energy is again dissipated. In a cycle, all VDDQ of

energy is converted into heat.


28

Whenever there is a conducting path, energy is dissipated if there is a potential difference

between the endpoints of the path (e.g. power supply terminal and the internal node in the

circuit). The amount of energy dissipated is VavgQ, where Vavg is the average potential

difference between the end points and Q is the amount of charge which flows through the

path. This implies that the circuit should switch adiabatically to avoid the energy dissipation.

Let us consider figure 2.2.b, where the power supply terminal swings gradually from 0 to

VDD, stays at VDD for a while and then swings back to 0. If X=0, and the initial charge on

capacitance is 0, then node Y follows the power supply to VDD during its upward swing.

Similarly, while discharging, potential of node Y follows the power supply terminal gradually

from VDD to 0, so that there is little potential difference across the path ( from the power

supply terminal to node Y ) in the whole transition process. Hence only a small amount of

energy is dissipated. The question is: Can an internal’s node voltage level follow the change

in the power supply terminal?

Let at the transition time of the power supply terminal from 0 to VDD (or from VDD to 0), and

the time constant in a conducting path is RC, where R is the effective resistance in the path

and C is the effective load capacitance. If the transition at the power supply terminal is

sufficiently slow, i.e., at >>RC, then the voltage drop between the power supply terminal

and node Y is small at any time instant during the transition, and hence, there is very low

power dissipation [8].

2.3 A SIMPLE ADIABATIC LOGIC GATE

In the following, we will examine simple circuit configurations which can be used for

adiabatic switching. Figure shows a general circuit topology for the conventional CMOS

gates and adiabatic components. To convert a conventional CMOS logic gate into an

adiabatic gate, the pull-up and the pull-down networks must be replaced with complementary

transmission gate (T-gate) networks. The T-gate network implementing the pull-up function

is used to drive the true output of the adiabatic gate, while -gate network implementing the

pull-down function drives the complementary output node. Note that all the inputs should be

available in complementary form. Both the networks in the adiabatic logic circuit are used to

charge-up as well as charge-down the output capacitance, which ensures that the energy


29

stored at the output node can be retrieved by the power supply, at the end of each cycle. To

allow adiabatic operation, the DC voltage source of the original circuit must be replaced by a

pulsed-power supply with the ramped voltage output.

Charge-up path

inputs

VDD Charge-down path

Cload

Figure - 2.3 (a)

Charge-down path Charge-up path

(back to power supply) Vout

inputs Cload2

VA Vout

Cload1

Figure - 2.3 (b)

Figure - 2.3 (a) General circuit Topology of a conventional CMOS Logic Gate

Figure - 2.3 (b) Topology of an Adiabatic Logic Gate implementing the same function

2.4 ADIABATIC COMPUTING

The energy CVDD2, which is consumed in the conventional CMOS circuits, is unavoidable

since the charge transfer from the supply and returned to the ground [9]. The current drawn

from the supply during a 0 1 transition is relatively large because of the large drain-

F

F

F

F


30

source voltage. If however, the supply voltage can be varied in a manner that would reduce

the drain current; the energy will be significantly reduced. This can be achieved by using

adiabatic circuits. Consider the circuit shown in the figure 2.4.a. This circuit is sometimes

referred to as a pulse power supply CMOS (or PPS CMOS) [9].

VA

constant

current

LOW Vout

Cload

Figure - 2.4 (a) Schematic of (Adiabatic) PPS CMOS inverter [9]

Its topology is very similar to that of the conventional CMOS inverter, except that its

supply is driven with a pulsed supply waveform VA.

Let us assume, the input is low and that the output (out) was initially low.

With the VA being low, the drain current = 0.

Now, as the voltage supply VA ramps us, the output follows the supply voltage VA.

The drain-to-source voltage is always small and so is the current drawn from the supply.

The adiabatic logic is also known as PULSED POWER SUPPLY (PPS) CMOS.

R

VA Vout

C

Figure - 2.4 (b) The RC model of PPS CMOS inverter


31

Assume that the supply is increasing in steps from 0 to VDD. Let us first

derive the energy per step as follows [11] =>

Between the ith

step and the next one, the supply voltage changes from Vi to Vi+1.

ID = I = C = (Vi+1 – Vo)/R

Solving this differential equation from t=ti (when the supply switches to Vi+1) to any time t <

ti+1, we get the following expression for the output voltage as a function of time.

Vo = Vi+1

Here, n is the number of step supply voltage.

Using above two equations, we obtain the current expression which is then used for the

derivation of the energy consumed per step =>

Estep = =

Estep =

Thus the energy consumed for one operation is nEstep.

Therefore, theoretically, if n is infinite (i.e., the VDD is a slow ramp), the energy goes to zero.

Etotal = nEstep =

The PPS-CMOS can be used for the complex Boolean function implementation. Hence, the

adiabatic circuits are operable only much lesser speed comparable to SCMOS circuits.

Another disadvantage is the requirement of a special type of power supply [9].


32

2.5 POWER SUPPLIES FOR ADIABATIC CIRCUITS

The design of a power clock generator is an important part of the whole adiabatic system

design. Many studies on adiabatic logic design have been made and various approaches have

been proposed. All of them require extra circuitry for one or more time-varying power

sources to provide extended charging time. There are methods such as those using either

inductive power supplies, step-wise charging through banks of capacitance tanks, or resonant

drivers, etc.

2.5.1 SELECTION OF POWER SUPPLIES FOR AN ADIABATIC

POWER SUPPLY

The adiabatic power supply needs an efficient energy recovery design which implies quality

factor Q of the power supply to be very high. Not only the Q should be high, it should be

proportional to the cycle time so that the energy dissipation in the power supply should also

decrease with the frequency. Otherwise, dissipation in the power supply itself will dominate

the logic circuit dissipation at lower frequencies. Most preferable technique is to use

sinusoidal voltage supply because of its ease to design as compared to pure trapezoidal wave.

The constant current charging needed can be approximated using a sinusoidal power supply.

To account for the non-constant charging current, the energy dissipation equation must be

multiplied by a constant shape factor £ (which takes the value of for a sine-shaped

current). The sinusoidal power supply can be realized using an external inductor. Thus an LC

resonant circuit with a resonance frequency of approximately 1/ is created and the

energy is oscillated between the external inductor and the capacitances to be switched.

In inductor based design [21] energy can be circulated between electrostatic field in the load

capacitor and magnetic field in the off-chip inductor. Analysis of this approach [21] shows

that by applying sinusoidal ramp, energy saved in the circuit reduced by the factor of

compared to pure trapezoidal wave and the total energy consumption including the power

supply is given by

Esinusoidal = CL VDD2

+ )


33

where and are the time constants of circuit branches of supply part and computing part

of the system respectively.

The energy dissipation Ediss results for three popular charging waveforms: a step, a linear

ramp and a sine wave are summarized in Table 2.1. As it is seen from the Table

2.1, the step input shows the typical ½ CV2 dissipation. The linear voltage ramp is the most

efficient adiabatic source because it is constant current. When the charging time T approaches

infinity, the dissipation approaches zero. The sine wave, adjusted to resonate between 0 and

V volts with a charging time of T, has been used in place of a linear ramp [8] because it is

simple to generate with a resonating inductor and capacitor circuit. The sine is much more

efficient than a step input if the period is sufficiently slow, but only 8/ or 81% efficient

compared to a ramp with the same rise time.

TABLE 2.1

THE EFFICIENCY OF THREE POPULAR CHARGING WAVEFORMS

SOURCE Ediss

V step(t)

CV2

V ramp(t)

Is =


34

[ sin( t

Thus, adiabatic charging is achieved when a charging waveform is more efficient than

(½)CV2 such as with ramp or sine waveforms. Energy recovery is achieved when some of the

(½)CV2

of the energy stored on the charged capacitive load is recovered and reused for later

charging.

Thus, it is often simpler to reduce the voltage V or reduce the switched capacitance C in order

to save power. However, when the limits of C and V have been reached (or they are fixed),

adiabatic charging proves to be the powerful tool for reducing the dissipation below (½)CV2.


35

Chapter

3

DESIGN OF TWO PHASE SINUSOIDAL POWER CLOCK

3.1 INTEGRATED POWER CLOCK GENERATORS

Our approach to power clock design is to integrate all power-clock switching transistors

and associated control circuitry on the same CMOS chip with low-energy logic. Only

small resonant-tank inductor(s) are added as external components. The power is

supplied from a low-voltage dc power source, a battery for example. Integration of

power clock generators with logic has a number of advantages:

The on-chip active devices are well suited for low-power, low-voltage power

conversion, and the device sizes are available for optimization at design time;

Power-clock distribution is improved because relatively large and detrimental

parasitic inductances are removed from the distribution network; bonding-wire

and other external parasitic inductances are absorbed by the external resonant-tank

inductor(s);

External discrete component count is minimized;

On-chip power-clock control circuitry can easily be implemented: sensing of power-

clock waveforms for control purposes is void of delays/noise introduced by the

chip I/O interface.

Common to the proposed power clock generators are the following characteristics:


36

An external inductor and the equivalent logic capaci tance form a resonant

tank. Power clock generator operates as high-frequency, resonant, unloaded dc/ac

inverter.

In order to minimize conduction losses, no active devices in the power clock

are placed in series with the inductor or in series with the logic.

All active devices in the power clock are soft-switched at zero voltage in order to

minimize switching losses.

Active control of the switching devices allows control over the power-clock

waveforms, simple synchronization, and simple generation of multiple phase-shifted

waveforms.

3.2 POWER CLOCK GENERATION

In adiabatic circuits, power and clock lines are mixed into a single power clock line, which has

both the functions of powering and timing the circuit. A DC to AC converter named power

clock generator is needed for the generation of the power clock signal. To evaluate the

performance of a power clock generator, the conversion efficiency is defined as the ratio of the

dissipated energy in the adiabatic core and the total delivered energy from the DC supply. The

LC resonant circuit is suitable for a power clock generator. L is an external inductor and C is

the distributed capacitance of the power clock line and it’s connected logic circuits all over

the chip. To have a stable frequency of oscillation, the equivalent on chip capacitance should

be constant and data independent, which is achieved in the adiabatic logic circuit due to its

differential nature. The first step in designing the power clock generator for an adiabatic

circuit is circuit modelling to determine the equivalent capacitance. This concept is described in

the following Section and illustrated by the example of our adiabatic CLA.

3.3 ADIABATIC LOGIC MODEL

For each phase, an approximate lumped-element model of the logic includes an equivalent


37

capacitor C to model energy storage, in series with a resistor R to model the losses. The

values of the model parameters R and C can be extracted from the simulation tests where an

external ideal sinusoidal voltage source is applied as the power clock. For a given clock

frequency f, and a logic activity, the power loss PL in the logic, and the RMS current IL

supplied to the logic by the power clock can be found from the test. Given PL and IL, the

model parameters can be found as:

Where V DD is the peak value of the applied power clock.

As an indication of the logic power loss relative to the maximum loss

that would occur in plain CMOS logic with the same C, we find

We have performed this test for our adiabatic CLA and extracted the equivalent R

and C for each power clock phase for the frequencies 10 MHz,20 MHz, 50 MHz and

100MHz. The results have been summarized in Table 3.1, where the tests were

performed for the maximum logic activity of the circuit.


38

Table 3.1

Results of modeling adiabatic for VDD=3.0 V

Frequ

ency

of

operat

ion of

the

power

clock

(MHz)

Power Clock Phase 1 Power Clock Phase 2

Power

(µwatt)

Current

(mA)

R (ohms) C (pF) Power

(µwatt)

Current

(mA)

R

(ohms)

C (pF)

10 0.2393 0.2918 2.8104

4.3807

5.4509 0.0660 1251.3

5

0.9908

20 1.2793 0.2808 16.224

7

2.1078

14.7131 0.1214 998.31

3

0.9112

50 4.3436 0.2775 56.405

8

0.8332

69.4907 0.2861 848.96

7

0.8590

100 9.6271 0.5186 35.795

6

0.7785

202.459 0.5868 587.974

1

0.8809

3.4 INTEGRATED RESONANT POWER CLOCK GENERATORS

Various circuit topologies for resonant energy recovery have been proposed for different

adiabatic logic styles and for different applications. They can be classified into two main


39

groups: asynchronous and synchronous power clock generators. Asynchronous power clock

generators are free running circuits that use feedback loops to self-oscillate without any external

timing signals. Fig. 4.1 illustrates two commonly used asynchronous power clock generators:

2N power clock generator. Many problems are associated with asynchronous structures. Their

oscillation frequencies are sensitive to their capacitive load variations in different cycles of the

system operation resulting in unstable frequency problems. In addition, in large systems, inputs

and outputs of each module must be in synchronization with other modules prohibiting the

integration of the adiabatic module driven by asynchronous power clock generators into a

larger non-adiabatic system. In these cases, the synchronous power clock generators can be

utilized as an efficient solution without having any of the above problems. Synchronous

power clock generators are synchronized to external time base signals usually available in

large systems.

2N synchronous power clock generators, similar to the asynchronous counterparts except that

the gate control signals are derived externally are shown. The capacitors CE1 and CE2 in

Figure 3.1 and 3.2 are external balancing capacitors to achieve more conversion efficiency.

We will show that the synchronous power clock generators are more energy efficient than

the asynchronous ones.

3.5 POWER CLOCK DESIGN

We design all two power clock generators for the adiabatic CLA, at 10MHz operating

frequency and 3.0V supply voltage, and compare the power dissipation and conversion

efficiency. Using the results in Table 2, we design each of the power clock generators by

placing simple resistors and capacitors equal to the extracted values instead of the adiabatic

adder.


40

Figure – 3.1 2N Asynchronous two phase power clock generators

Figure - 3.2 2N Synchronous two phase power clock generators


41

CK1 1/fc

CK2

Figure – 3.3 Pulse signals to a synchronous power clock generator.

Then this simple circuit can be quickly designed and simulated to find the optimum design.

The value of L is determined by the required frequency and the extracted capacitance. The

oscillating frequency for the 2N power clock generators is determined by

Where C is the equivalent capacitance of each phase. After simulating and optimising the

power clock generator with the simple RC model, the designed power clock generator is

connected to the adiabatic CLA and simulated again. In this stage, slight modifications may

be needed to optimise the design for the highest achievable conversion efficiency.

If we talk of only 1-n clock generator circuit, to determine the switch Qrms current, we observe

that the switch current during the D/ interval is increasing from zero approximately as a

linear function of time. During the switch-on time, energy is added from the dc power source

to the resonant tank.

When the switch Q is turned off, the energy is dissipated during the oscillation. For a

sustained steady state oscillation, we have the required energy balance equation given

approximately by:

Using the above equations, we solve for the switch current at the end of the switch on

time and the required switch duty ratio D,


42

The switch rms current is then given by:

For Adiabatic CLA operating at 10 MHz, for phase 1, value of D came out to be 0.01124 and

for phase 2, value of D came out to be 0.1118. The waveform for synchronous 2n power

generator scheme is as follows

Figure – 3.5 Simulation results of 2N synchronous power clock generators


43

The results, summarised in Table 3.2, indicate that with synchronous power clock

generators, higher conversion efficiencies can be achieved. Between the two synchronous

schemes, the 2N power clock generator is simpler, more energy efficient, and resulting in the

higher conversion efficiency of 53.26%.

Table 3.2

Power dissipation summary of adiabatic CLA with different power dock generators at

10MHz operating frequency and 3.0V supply voltage

Power clock generator Synchronous Asynchronous

2N 2N

Power dissipation of a CLA core 5.65 µW 8.43 µW

Total delivered power 10.6 µW 108.44 µW

Conversion efficiency 53.26% 7.774%

232


44

Chapter

4

DESIGN AND ANALYSIS OF LOW POWER CMOS

STRUCTURES

4.1 PASS TRANSISTOR ADIABATIC LOGIC

(PAL)

Pass Transistor Adiabatic Logic (PAL Logic) refers to the low power scheme that has been

used in the present project. It is an adiabatic Complimentary Metal Oxide Semiconductor

(CMOS) logic based on the principal of recycling of energy between an AC power clock and

the Logic. Common to all the adiabatic (low power) logics is the periodic exchange of energy

between the power clock and the logic. The path for the energy transfer depends upon the

logic. Logic evaluation follows one of the several possible schemes including the retractile

cascade, regenerative or memory scheme. Memory schemes with partial energy recovery are

preferred because of much simpler and area efficient implementation. Also, in the memory

scheme, each logic stage performs a memory function so that logic outputs may remain valid

for use in the next stage even though the logic inputs do not remain constant. Assuming

standard CMOS logic implementation, this leads to a loss of C|Vt|2, where Vt is the device

threshold voltage (which is of the order of ~1V for 3V supply), accompanies each logic

transition when the memory is being erased. Still, its way less than the CVdd2 loss occurring

in the conventional CMOS logic.


45

Figure 3. (a) – Schematic of an A.B+C block implemented using the PAL design logic

4.2 PAL gates

Pass Transistor Adiabatic Logic is a dual rail adiabatic logic with a relatively low gate

complexity and it operates with a two phase power clock. It has memory function performed

by a pair of cross coupled PMOS gates and the logic function performed by a pair of true and

complimentary pass transistors’ NMOS functional blocks (f, f’). Referring to the figure---- ,

the implementation of the function A.B+C has been shown using the PAL logic. The power is

supplied through a power clock (constructed as described in the sections -----). The inputs

make a conduction path, when the sinusoidal power clock is rising, from the input to one of

the output nodes (f or f’). The other node will be tristated and kept to zero volts by its load

capacitance. This, in turn, causes one of the PMOS transistor to conduct and charge the node

that should go to logic one, up to the peak of he power clock. The output state is valid at

around the peak of the power clock. The power clock will then ramp down from the top

towards the zero value, recovering the energy stored in the output node capacitance.

4.3 PAL gates cascaded

Cascade of logic gates is provided with alternately connecting it to the power clock (PC) and

its 180 shifted signal power clock (PC’). All odd logic states are supplied by the sinusoidal


46

voltage PC and all the even ones by PC’. There are two phases, the evaluate phase and the

discharge phase. When the PC is rising it’s the evaluate phase of the gate, when it’s

discharging, it’s the discharge phase. So, connecting the cascaded gates with two power

clocks differing in phase by 180 we ensure that the discharge phase of all the odd phases

coincides with the evaluate phase of the even phases and vice versa. The cascade of four

inverters has been shown in the figure ----- and the corresponding waveform in figure-----

Figure 3. (b) – Schematic of four PAL NOT gates connected in cascade using two phase power clock


47

Figure 3. (c) – Waveforms for the schematic in fig. 3. (b)

All the design structures using CMOS Pass Transistors Adiabatic Logic (PAL) were designed

and simulated using UMC 0.18µm CMOS technology and 3V supply at an operating

temperature of 27C. Cadence Corporation based tool known as Virtuoso has been used for

all design and simulations. The basic cells used like the NAND gate, NOR gate, Inverter,

Buffer, XOR gate has been designed using appropriate sizing.

The Power Clock in all the presented gate simulations has been given using a sinusoidal pulse

generated using the concepts developed in chapter 3. Later, after the whole configuration of

the circuit, the main Power Clock has been replaced by the designed Power Clock which has

been configured using all the bulk circuit parameter of the final circuit in order to generate

the sinusoidal power clock.

In all the simulation results shown below, we have the power clock input then the input(s)

followed by the output.


48

4.4.1 Design and Simulation of Inverter using conventional

CMOS and PAL logic:

The one input inverter was designed using the conventional CMOS and the PAL technology

on the Virtuoso Design tool using the 0.18 µm CMOS technology and 3V supply.

Figure 4.1 (a) – Schematic of Inverter/Buffer based on PAL technology

Figure 4.1 (b) – Simulation result of Inverter based on conventional CMOS technology.


49

Figure 4.3 (c) – Simulation result of Inverter based on PAL technology.

Table 4.1

Comparative Table of Power Dissipation of CMOS/PAL Inverter on

various frequencies

Sl.

No.

Frequency of the

Power Clock

(MHz)

Power Dissipation using

standard CMOS inverter

(watt)


PAL inverter (watt)

1. 10 0.00000236 0.000000055

2. 20 0.00000472 0.000000221

3. 50 0.0000118 0.00000136

4. 100 0.0000236 0.00000529


50

4.4.2 Design and Simulation of Two Input NAND using

conventional CMOS and PAL logic:

The two input NAND gates based on conventional and PAL logic is designed and simulated

on the Cadence Virtuoso Analog Design environment using 0.18 µm conventional CMOS

technology and a supply voltage of 3V.

Figure 4.2 (a) - Schematic of two inputs NAND gate based on PAL technology

Figure 4.2(b) - Simulation result of two inputs NAND gate based on conventional

CMOS technology


51

Figure 4.2 (c) - Simulation result of two inputs NAND gate based on PAL technology

Table 4.2

Comparative Table of Power Dissipation of CMOS/PAL two input NAND

gate on various frequencies

Sl.

No.

Frequency of the

Power Clock

(MHz)


standard CMOS two input

NAND gate (watt)


PAL two input NAND gate

(watt)

1. 10 0.00000121 6.09E-08

2. 20 0.00000242 0.000000237

3. 50 0.00000604 0.00000144

4. 100 0.0000121 0.00000559


52

4.4.3 Design and Simulation of Two Input NOR gate using CMOS

and PAL logic:

The two inputs NOR was designed using the conventional CMOS and the PAL technology on

the Virtuoso Design tool using the 0.18 um CMOS technology and 3V supply.

Figure 4.3 (a) - Schematic of two inputs NOR gate based on PAL technology.

Figure 4.3(b) - Simulation result of two inputs NOR gate based on conventional CMOS

technology.


53

Figure 4.3 (c) - Simulation result of two inputs NOR gate based on PAL technology

Table 4.3

Comparative Table of Power Dissipation of CMOS/PAL Two Input NOR


Sl.

No.

Frequency of the

Power Clock

(MHz)



NOR gate (watt)


PAL two input NOR

gate(watt)

1. 10 0.00000122 3.49E-08

2. 20 0.00000243 0.000000134

3. 50 0.00000607 0.000000821

4. 100 0.0000121 0.00000329


54

4.4.4 Design and Simulation of Two Inputs XOR gate using

CMOS and PAL logic:

The two inputs XOR was designed using the CMOS and the PAL technology on the Virtuoso

Design tool using the 0.18 µm CMOS technology and 3V supply.

Figure 4.4 (a) - Schematic of two inputs XOR gate based on PAL technology.


55

Figure 4.4 (b) - Simulation result of two inputs XOR gate based on conventional CMOS

technology.

Figure 4.4 (c) - Simulation result of two inputs XOR gate based on PAL technology


56

Table 4.4

Comparative Table of Power Dissipation of CMOS/PAL Two Input XOR


Sl.

No.

Frequency of the

Power Clock

(MHz)



XOR gate (watt)


PAL two input XOR gate

(watt)

1. 10 0.00000141 8.91E-08

2. 20 0.00000282 0.000000346

3. 50 0.00000705 0.00000208

4. 100 0.0000141 0.00000823

4.4.5 Design and Simulation of Three Inputs A.B+C gate using

CMOS and PAL logic:

The three inputs A.B+C is designed using the CMOS and the PAL technology on the

Virtuoso Design tool using the 0.18 µm CMOS technology and 3V supply.


57

Figure 4.5 (a) - Schematic of three inputs A.B+C gate based on PAL technology.

Figure 4.5 (b) - Simulation result of three inputs A.B+C gate based on PAL technology


58

Chapter

5

DESIGN AND IMPLIMENTATION OF 8 BIT CARRY

LOOK AHEAD ADDER USING THE PASS

TRANSISTOR ADIABATIC

LOGIC AND ANALYSIS OF POWER DISSIPATION

PATTERN OF THE CIRCUIT

5.1 Carry Look Ahead Adders (CLA):

The ripple carry adder has a limitation of a huge propagation delay in propagating the carry

till the end. The carry look ahead adder solves this problem by calculating the carry signal in

advance, based on the inputs. The result is a reduced carry propagation time.

We have to manipulate the Boolean expression dealing with the full adder. The propagation P

and the generate G in a full adder is given as:

Pi = AiBi Carry Propagate

Gi = Ai.Bi Carry Generate.


59

Since both the P and G signals only depend upon the inputs, hence they will be valid just

after one gate delay.

Expression for output sum and carry are given as:

Si = Pi Ci-1

Ci+1 = Gi + Pi.Ci

The general expression for carry is

Ci+1 = Gi + Pi.Gi-1 + Pi.Pi-1.Gi-2 + …. Pi.Pi-1…. P2.P1.G0 + Pi.Pi-1… P1.P0.C0.

The general circuit based on which, the conventional CMOS and the PAL logic Carry Look

Ahead adders were made for analysis is shown in figure 5.1

Figure 5.1 – Circuit diagram of an 8 bit carry look ahead adder. The symbols used have

their usual meanings.


60

5.2 Design and Implementation of an 8 bit carry Look Ahead

adder using conventional CMOS and the PAL technology

The 8 Bit Carry Look Ahead adder circuit which is a benchmark circuit is designed based on

the conventional CMOS technique and the Pass Transistor Adiabatic Logic using the

Cadence Virtuoso analog design environment using 0.18 µm CMOS Technology on a supply

voltage of 3V.

Figure 5.2 – Schematic of an 8 bit carry look ahead adder implimented using the PAL

cells as described in chapter 4.


61

In figure 5.2, stands for XOR gate, stands for AND gate, stands for logic AB+C and rest

unmarked blocks are buffers.

The circuit was simulated at 4 frequencies 10,20,50 and 100 MHz. The simulation for the

circuit for 10 MHz is shown in following figure. Input vectors for the circuit were

A=10010101, B=10111100. Since the circuit consists of 6 levels. Thus the output was present

at the end of 3rd

clock. The marker shows the position of the end of 3rd

clock.

Output waveforms are in sequence PCLK, /PCLK, S7 to S0 and then Cout.

Value of output = S = 01010001

Cout = ‘1’


62

Figure.5.3- Output waveforms for PAL 8 bit CLA operating at 10 MHz


63

5.3 Observations after Simulation and calculation of power

dissipation by the conventional CMOS circuit and the Pass

Transistor Adiabatic Logic on the basis of the results.

The circuit designed using the PAL cells to make the 8 bit carry look ahead adder is being

supplied with a power clock made using the concept explained in chapter 3. To set the R and

C parameters in the two phased clocks, we first connect the circuit to an external source of

sinusoidal signal and the bulk parameters are calculted by using the power dessipation and

the current data from this. After finding the R and C values for the circuit we replace the

external source with the power clock.

Table 5.1

Frequency

of

operation

of the

power

clock

(MHz)

Power Clock

Phase 1

Power Clock Phase

2

Total

power

dessipation

in the PAL

circuit

(µwatt)

Total power

dissipation

in

conventional

CMOS

circuit

(µwatt)

Decrease

in power

dissipation.

(%) Power

(µwatt)

Current

(mA)

Power

(µwatt)

Current

(mA)

10 0.2393 0.2918 5.4509 0.0066 8.3115 28.8792 71.22

20 1.2793 0.2808 14.7131 0.1214 20.608 57.6921 64.28

50 4.3436 0.2775 69.4907 0.2861 85.230 144.07 40.84

100 9.6271 0.5186 202.4596 0.5868 239.832 288.0866 16.75


64

Figure 5.3 - Comparative chart for the power dissipation in 8 bit CLA implemented

using the PAL logic and using the conventional CMOS. The X-axis represents the

frequency in MHz and the Y-axis represents the power dissipated in µwatts.

It can be seen that we get a power saving of up to 71.22% over the conventional CMOS logic

at a 10 MHz frequency of power clock if we use the PAL. We observe that we get a

progressively increasing amount of power dissipation with both the techniques as we increase

the frequency. However, the power dissipation in PAL logic is always less as compared to the

conventional CMOS. Beyond 100 MHz it’s observed that the power dissipation increases by

using the PAL logic, due to the short duration of the PAL evaluation pulse.

5.4 Scope of Future Work:

The present work can be extended in various directions as shown below

(a). To perform digital logic I CMOS in a truly adiabatic fashion requires that the logic

transitions be driven by a quasi trapezoidal power clock voltage waveform, which must be


65

generated by a resonant element with a very high Q (Quality factor). Recently MEMS

resonators have attained very high Q factor and are becoming widely used in communication

on chip.

(b). The high cost-per weight of launching computing related power supplies solar panels and

cooling systems into orbit imposes a demand for adiabatic power reduction in space craft in

which these components weigh a significant fraction of total spacecraft weight.

(c). There is a huge scope of improvement in the design and implementation of the power

clock for the adiabatic circuit. The synchronous power clock can only achieve efficiency up

to 58% and hence becomes the major source of power dissipation in the circuit. Work can be

done in this regard.


66

REFERENCES

[1]. Abdellatif Bellaouar and Mohamed I. Elmasry, Low-Power Digital VLSI Design Circuits

and System, Kluwer Academic Publishers, 1995, ISBN# 0-7923-9587-5.

[2]. V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design, John Wiley &

Sons Ltd., 2006, ISBN# 0-470-01023-1.

[3]. A. P. Chandrakasan and R.W. Brodersen, “Minimizing Power Consumption in Digital

CMOS Circuits”, Proceedinds of the IEEE, VOL. 83, No. 4, April 1995.

[4]. Sung-Mo Kung and Yusuf Leblebici, CMOS Digital Integrated Circuits, Tata MaGraw

Hill Edition, 2003, ISBN# 0-07-053077-7.

[5]. J. Kao, S. Narendra, and A. Chandrakasan, “Sub-threshold leakage modelling and

reduction techniques, “Proc. ICCAD, pp. 141-148, Nov. 2002.

[6]. J.M.C. Stock, “Technology Leverage for Ultra-Low Power Information Systems”, IEEE

Symposium on low power electronics, Tech. Dig., pp. 52-55, October 1994.

[7]. SAED G. YOUNIS, “Asymptotically Zero Energy Computing Using Split-level Charge

Recovery Logic,” PhD thesis, 1994.

[8] KAUSHIK ROY, YIBIN YE, “Ultra Low Energy Computing using Adiabatic Switching

Principle” ECE Technical Reports, Purdue University, Indiana, March, 1995.

[9] Yan He, Hao Min, “Adiabatic Circuit Applied for LF Tag Auto-ID Labs” White Paper,

WP-HARDWARE-041

[10] ATHAS, W.C, SVENSSON, L.J., and TZARTZANIS, N: “A resonant signal driver for

two-phase, almost non-overlapping clocks”, Proceedings of IEEE international symposium

on Circuits and Systems, May 1996, Vol. 4, pp. 129-132


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Pass transistor adiabatic logic for low power VLSI design