Background: VLSI Courses at Lafayette ï½ ECE 425 - VLSI Circuit Design ï½ Original form: “tall thin designerâ€‌  VLSI Processing  CMOS Transistor Characteristics

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Text of Background: VLSI Courses at Lafayette ï½ ECE 425 - VLSI Circuit Design ï½...

  • Introduction and OverviewMotivation - The Digital ParadoxDigital VLSI chips & applications are pervasive in:Computer SystemsTelecommunicationsConsumer ElectronicsAutomotive ElectronicsBUT analog concerns more important than ever!Must connect digital chips to an analog worldMany chips now combine analog and digital circuitsDesigners must consider analog effects in digital circuitsBottom Line: Undergraduate VLSI students need exposure to both analog and digital concerns

    ObjectivesAdd analog to broaden a digital course Teach concepts as extension of digital analysis and design methodsFocus on data conversion - useful to both analog and digital designersMaintain strong digital design focusLay foundation for further study in analogBackground: VLSI Courses at Lafayette ECE 425 - VLSI Circuit DesignOriginal form: tall thin designerVLSI ProcessingCMOS Transistor CharacteristicsParasitic EffectsCustom LayoutStandard-Cell ASICs (Application-Specific Integrated Circuits)ASIC Design using Hardware Description Languages (HDLs) and CAD ToolsStudent design project: Tiny ChipComplete 2.2mm X 2.2mm chipFabrication by MOSIS (MOS implementation Service) Educational ProgramECE 426 VLSI System DesignFollow-on to ECE 425More coverage of HDL-based System DesignTesting of fabricated MOSIS chipsExtending ECE 425New focus on Data ConversionDigital / Analog ConversionComparatorsAnalog / Digital ConversionContinued focus on DesignBasic cell analysis and layoutASIC-style HDL-based designFull chip design (mixed analog & digital)

    New Design ProjectsD/A ConverterVoltage Scaling designHierarchical LayoutA/D ConverterSuccessive Approximation circuit: designed using HDL / standard cellsD/A Converter used as building blockUses dynamic analog comparator supplied by instructorAssembled to complete chip

    Lecture Topic

    Laboratory

    CMOS Processing

    Schematic Editing / Simulation

    Device Physics; MOS Transistor Characteristics

    Parasitic Components

    Basic Gate Layout

    Layout and Design Rules

    Extraction, Simulation, and Layout Verification

    Extraction/Simulation/LVS

    Hierarchical Layout

    Voltage-Scaling D/A Conversion

    Layout Mini-Project: 4-bit Voltage Scaling DAC

    ASIC Layout Styles: Std. Cells, Gate Arrays, FPGAs

    Combinational Logic: Gate Design and Layout

    Comb. delay and power dissipation; testing

    Comb. Design with HDLs & Logic Synthesis

    HDL Design (Combinational)

    Sequential Logic: Latch & Flip-Flop Design

    Sequential Circuits and Clocking Schemes

    Sequential Design with HDLs & Logic Synthesis

    HDL Design (Sequential)

    Sequential Testing & Design for Test

    Successive-Approximation A/D Conversion

    Final Project: 4-bit Successive Approximation ADC

    Clocked Auto-Centering Comparators

    Digital VLSI System Design

    Analog VLSI Overview

  • Mixed-Signal Design ActivitiesVoltage-Scaling D/A ConverterComparator Design (provided by instructors)Successive Approximation A/D ConverterComparatorClock Generator Logic

  • Results and ConclusionsFinal Chip LayoutFabrication & Testing Results - Fall 200115 students completed 8 student chip designs7 submitted for fabrication to MOSIS7 chips worked as desginedConclusionsSuccessfully integrated analog concerns in previously all-digital courseStudents created working mixed signal (A/D) chips

    Future WorkAdditional analog coverageBetter integration of testing and design-for test

    More Information Available at:http://foghorn.cadlab.lafayette.edu/ece425

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