Introduction to CMOS VLSI Design CMOS Transistor Theory

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  • Slide 1
  • Introduction to CMOS VLSI Design CMOS Transistor Theory
  • Slide 2
  • CMOS VLSI DesignMOS devicesSlide 2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models
  • Slide 3
  • CMOS VLSI DesignMOS devicesSlide 3 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C ( V/ t) -> t = (C/I) V Capacitance and current determine speed Also explore what a degraded level really means
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  • CMOS VLSI DesignMOS devicesSlide 4 MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion
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  • CMOS VLSI DesignMOS devicesSlide 5 Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V ds = V d V s = V gs - V gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation
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  • CMOS VLSI DesignMOS devicesSlide 6 nMOS Cutoff No channel I ds = 0
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  • CMOS VLSI DesignMOS devicesSlide 7 nMOS Linear Channel forms Current flows from d to s e - from s to d I ds increases with V ds Similar to linear resistor
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  • CMOS VLSI DesignMOS devicesSlide 8 nMOS Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source
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  • CMOS VLSI DesignMOS devicesSlide 9 I-V Characteristics In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving?
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  • CMOS VLSI DesignMOS devicesSlide 10 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel =
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  • CMOS VLSI DesignMOS devicesSlide 11 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C =
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  • CMOS VLSI DesignMOS devicesSlide 12 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ox WL/t ox = C ox WL V = C ox = ox / t ox
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  • CMOS VLSI DesignMOS devicesSlide 13 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ox WL/t ox = C ox WL V = V gc V t = (V gs V ds /2) V t C ox = ox / t ox
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  • CMOS VLSI DesignMOS devicesSlide 14 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v =
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  • CMOS VLSI DesignMOS devicesSlide 15 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = E called mobility E =
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  • CMOS VLSI DesignMOS devicesSlide 16 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = E called mobility E = V ds /L Time for carrier to cross channel: t =
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  • CMOS VLSI DesignMOS devicesSlide 17 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = E called mobility E = V ds /L Time for carrier to cross channel: t = L / v
  • Slide 18
  • CMOS VLSI DesignMOS devicesSlide 18 nMOS Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross
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  • CMOS VLSI DesignMOS devicesSlide 19 nMOS Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross
  • Slide 20
  • CMOS VLSI DesignMOS devicesSlide 20 nMOS Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross
  • Slide 21
  • CMOS VLSI DesignMOS devicesSlide 21 nMOS Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current
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  • CMOS VLSI DesignMOS devicesSlide 22 nMOS Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current
  • Slide 23
  • CMOS VLSI DesignMOS devicesSlide 23 nMOS Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current
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  • CMOS VLSI DesignMOS devicesSlide 24 nMOS I-V Summary Shockley 1 st order transistor models
  • Slide 25
  • CMOS VLSI DesignMOS devicesSlide 25 Example Example: a 0.6 m process from AMI semiconductor t ox = 100 = 350 cm 2 /V*s V t = 0.7 V Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2
  • Slide 26
  • CMOS VLSI DesignMOS devicesSlide 26 pMOS I-V All dopings and voltages are inverted for pMOS Mobility p is determined by holes Typically 2-3x lower than that of electrons n 120 cm 2 /V*s in AMI 0.6 m process Thus pMOS must be wider to provide same current In this class, assume n / p = 2
  • Slide 27
  • CMOS VLSI DesignMOS devicesSlide 27 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion
  • Slide 28
  • CMOS VLSI DesignMOS devicesSlide 28 Gate Capacitance Approximate channel as connected to source C gs = ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 fF/ m
  • Slide 29
  • CMOS VLSI DesignMOS devicesSlide 29 Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff C g for uncontacted Varies with process
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  • CMOS VLSI DesignMOS devicesSlide 30 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V DD
  • Slide 31
  • CMOS VLSI DesignMOS devicesSlide 31 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V DD V g = V DD If V s > V DD -V t, V gs < V t Hence transistor would turn itself off nMOS pass transistors pull no higher than V DD -V tn Called a degraded 1 Approach degraded value slowly (low I ds ) pMOS pass transistors pull no lower than V tp
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  • CMOS VLSI DesignMOS devicesSlide 32 Pass Transistor Ckts
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  • CMOS VLSI DesignMOS devicesSlide 33 Pass Transistor Ckts
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  • CMOS VLSI DesignMOS devicesSlide 34 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay
  • Slide 35
  • CMOS VLSI DesignMOS devicesSlide 35 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width
  • Slide 36
  • CMOS VLSI DesignMOS devicesSlide 36 RC Values Capacitance C = C g = C s = C d = 2 fF/ m of gate width Values similar across many processes Resistance R 6 K * m in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 ) Or maybe 1 m wide device Doesnt matter as long as you are consistent
  • Slide 37
  • CMOS VLSI DesignMOS devicesSlide 37 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter
  • Slide 38
  • CMOS VLSI DesignMOS devicesSlide 38 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter
  • Slide 39
  • CMOS VLSI DesignMOS devicesSlide 39 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter
  • Slide 40
  • CMOS VLSI DesignMOS devicesSlide 40 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter d = 6RC