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  • 7/22/2019 c.vijaya Cmos Vlsi Download


    Unit 5

    5.1: CMOS Process Flow: The difference between new and old process flow are as

    mentioned here. Minimum length of the channel, L min < 0.35 micro m in the case of

    sub micron CMOS process. The device isolation technique is Shallow Trench Isolation

    (STI) instead of local oxidation of Silicon (LOCOS). n+ poly is employed for NMOS and

    p+ poly for PMOS formulation. Drains are lightly doped to reduce short channel effects.

    Silicided source / drain / gates are used to reduce parasitic resistances. NMOS & PMOS

    are developed as surface devices and thus PMOS is not a buried channel device.

    The steps in CMOS Process Flow:

    Step 1: The Process starts with p type wafer or p+ wafer with p- epitaxial layer. Thin

    oxide and nitride are deposited. The purpose of deposition is for active areas patterning.

    Photo resist is deposited and patterned on its top. Exposed area of nitride is then

    removed. The step is shown in fig. 5.1 (a)

    Step 2: Silicon areas that are exposed are etched. It is the part not covered by photo resist.

    Thus, shallow trenches are formed as shown in fig 5.1 (b)

    fig. 5.1 (a)


    fig. 5.1 (b)

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    Step 3: Shallow trenches formed in step 2 are filled with Chemical Vapor Oxide (CVD)

    (STI). The process is known as Chemical Mechanical Polishing (CMP). Thus, the top is

    now flat as in fig. 5.1 (c).

    Step 4: Implants are used to make body of the PMOS (n well) transistors. Fig. 5.1

    (d) shows the wafer after implant.

    Step 5: Patterning the polysilicon gates on the top of the wafer is carried out in this step.

    The effect of it is shown in fig. 5.1 (e).

    Step 6: Light and shallow implants are used in lightly doped drain (LDD) MOSFET

    formulation as in fig. 5.1 (f)

    fig. 5.1 (c)

    fig. 5.1 (d)

    fi . 5.1 (e)

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    Step 7: in this step, lateral oxide spacer adjacent to the gate poly is formed. Implants to

    heavily doped gates, sources and drains are formed. p+ poly is used in PMOS

    formulation. The result of the same is shown in fig. 5.1 (g).

    Step 8: in this last step, silicide is deposited. It is combination of silicon and tungsten


    There are certain advantages of CMOS Process. CVD or STI enables to define smaller

    openings in the top of the wafer. This leads to smaller active area windows. Thus,

    effective encroachment on the device width is reduced. Now, MOSFET can be placedcloser together. p+ poly used in PMOS formulation results in surface device. Because of

    which, conduction between the source and drain is along the oxide / semi conductor

    interface. And not through buried channel. In surface device, threshold voltage of the

    PMOS is easier to set precisely. There is no need to counter dope the channel for the

    purpose. It is also observed that short channel effect less severe. Use of Silicide produces

    fi . 5.1 f

    fig. 5.1 (g)

    fig. 5.1 h)

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    devices with significantly less parasitic series gate and source / drain resistances.

    However, Silicide complicates the process. Surface device reduces mobility and increase

    in flicker noise.

    5.2.1: Implementation of Capacitors: four types of capacitors will be considered in the

    discussion to follow. They are MOSFET as a capacitor, Native / natural MOSFET

    capacitor, Floating capacitor and Metal capacitor.

    Using MOSFET as a capacitor: As shown in fig. 5.2, source, drain and body are

    connected to ground. Gate is available as one terminal. The capacitor thus formed is a

    unipolar capacitor.

    As in fig. 5.3, VGS should be much greater than 400mV for the device to behave as a

    capacitor. If it is not satisfied, capacitor exhibits non linearity.

    Using native MOSFET capacitor: It is formed by laying out poly over n+ active in n well.

    It is also unipolar capacitor. The symbolic representation of it is shown in fig.

    fig. 5.2

    fig. 5.3

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    The laying out of native capacitor is shown in fig. 5.5. poly over n+ active in n well

    reduces threshold voltage. Thus, it suits for low voltage applications. The capacitance

    versus voltage in native capacitor is shown in fig. 5.6. The threshold voltage is 100mv.

    The floating Capacitor: here, two PMOS are laid together, adjacent or inter-digitated in

    the same n well. Capacitors are in series as in fig. 5.7. the increase in voltage at A causes

    accumulation of charges under the left side MOSFET gate oxide. Equal and opposite

    charge is stored in B MOSEFT. Minimum voltage requirement is shown in fig. 5.8

    fig. 5.4

    fig. 5.5

    fig. 5.6

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    The Metal Capacitor: Metals (copper) have large layout area. Thus, fringe capacitance

    contribution is small. The capacitance between the two plates is given by C12=area x

    capacitance per area. Thickness of the metal increases if it is away from substrate. The

    layout is shown in fig. 5.8

    The two parallel plates in parallel plate capacitor are metal 1 and metal 2. The capacitor

    is also referred to as metal1-metal2 capacitor. The typical capacitance per micro m 2area

    is 25-50aF/micro m2. It requires an area of 100 micro m x 200 micro m for 1pF capacitor.

    Capacitor with large bottom plate suffers from parasitic capacitance. It is the capacitance

    between metal1 and substrate. Its value is significant and 80 % to 100 % of actual

    capacitance. The presence of parasitic capacitance results in slow response from a circuit

    and waste of power.

    Vx VDDfig. 5.8

    fig. 5.7

    fig. 5.8

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    The 4 layers Metal Capacitor is shown in fig. 5.9. the total capacitance is given by

    C=C12 + C23 + C34. 50aF/micro m2requires area of 100 micro m x 200/3 = 66 micro m

    for 1pF capacitor. Thus, reduces area by 1/3rd

    . Capacitance between metal 1 and substrate

    is now less, in comparison with total capacitance C and hence there is reduction in

    parasitic capacitance.

    There is possibility of metal1 only capacitor also. Two metal pieces are placed close to

    each other in the layer above substrate. There is fringe capacitance, in metal1 only

    capacitor. It is because of minimum width and distance between two pieces of metal1. If

    0.5 micro meters is the width and distance, effect is predominant. Effect of fringe

    capacitance is more than parasitic capacitance. The layout of metal1 only capacitor and

    fringe effect is shown in fig. 5.10 and 5.11 respectively. Fringe capacitance is due to

    electric field terminating on the close adjacent metal.

    fig. 5.9

    fig. 5.10

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    Problem 1: Estimate the area of metal1 only 1 pF capacitor in a layout as shown in fig.

    5.P1. Also determine parasitic capacitance.


    Capacitance per 1 micro m2 is 25aF is given.

    Thus, for 1pF, area = 1pF/25aF = 40000 micro m2

    Parasitic capacitance (usually 50%) =1pF/2 = 0.5pF

    Capacitance With Via is yet another capacitance layout. Lateral capacitance between

    vias, as in metal1- metal4 is shown in fig. 5.12. The capacitance per unit area increases,

    though not linearly. It is of the order of 200aF/micro m2. The bottom plate capacitance

    remains at 15aF/micro m2. For higher levels of metal, the rules for width and spacing

    between the metals are different. Thus, thumb rule for implementation of capacitance in a

    mixed signal circuit is lateral capacitance with several layers of metal and vias.

    fig. 5.11

    fig. 5.P1

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    Example 2: Estimate the area of lateral capacitor for 1 pF capacitor in a layout.Solution:

    Capacitance per 1 micro m2 is 200aF because of lateral capacitance. .

    For 1pF, area = 1pF/200aF=5000 micro m2

    5.2.2: Properties of Resistors: the typical properties of variety of resistors is listed intable 3.1

    One of the properties of resistor is its Voltage Coefficient of Resistor (VCR). It is due to

    mismatch in voltages across two equal valued resistors even when same voltage is

    applied across each resistor. Mismatch = VCR x difference in voltages across two

    resistors. Extension of depletion region into n type material in n well, leads to VCR

    problem. The Mismatch % is the variation in the same valued resistors.RR/

    fig. 5.12

    Table 5.1

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    Temperature Coefficient of Resistor (TCR) is variation of resistance value with

    temperature. All these errors will lead non linear behavior of resistor. Polysilicon, p+, n+

    poly. p+, n+ diffusion are the various types of resistors with and without Silicide. The

    error is found to be less in polysilicon. Hence it is used in high precision circuits, such as


    Example 3

    Determine the minimum and maximum area required to implement resistor of 1Kohm

    in a Submicron CMOS process and also name the resistor type.


    Minimum Resistance per micro m2is for p+ silicide

    Area = 1k/2=500 micro m2

    Thus requires maximum area.

    Maximum Resistance per micro m2 is for n wellArea = 1k/500=2 micro m


    Thus requires minimum area

    Example 4