Introduction to CMOS VLSI Design kogge/courses/cse40462-VLSI-fa18/www/Public/...¢  CMOS VLSI Design

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    Introduction to CMOS VLSI

    Design

    VLSI Circuit Layout: Standard Cells

    Peter Kogge University of Notre Dame

    Fall 2015, 2018

    Based on material from Prof. Jay Brockman, Joseph Nahas, University of Notre Dame

    Prof. David Harris, Harvey Mudd College http://www.cmosvlsi.com/coursematerials.html

    CMOS VLSI DesignLayout Slide 2

    Outline

     Design Rule Review  Layout Styles  Standard Cell Layouts  Wiring Tracks  Stick Diagrams  Euler Paths  Tracks and Spacing's  Area Estimation

  • 2

    CMOS VLSI Design

    Audience Review Questions

     What is a “Design Rule”?

     What is “λ”?

     Why is this a useful unit of measure?

    Layout Slide 3

    CMOS VLSI Design

    Design Rules from Ed. 3’s Back Cover

    Layout Slide 4

  • 3

    CMOS VLSI Design

    A Conservative Set of Simpler Rules

    Layout Slide 5

    Audience Question: Why are we using 4λ here, vs 3λ from rules

    CMOS VLSI Design

    Layout Styles

    Layout Slide 6

  • 4

    CMOS VLSI Design

    Layout Styles

     Custom – Random transistor and other component positioning and

    wiring.  Standard Cell

    – Logic gates “pre-designed” • Power rails (Vdd and Vss) on top and bottom • Common N and P wells

    – PMOS transistors on top – NMOS transistors on bottom

    – Gates wired together automatically using Place and Route tool.  Pitch-Matched Data Path

    – Custom or automatic layout of logic in data channels. • Typically 8, 16, 32, or 64 bits wide.

    – Channels match each-other and mesh.  Memory will be discussed later

    Layout Slide 7

    CMOS VLSI DesignLayout Slide 8

    Layout Styles: An ND 12 bit Processor

    standard cell

    datapath

    Cells

    Wiring Channel

  • 5

    CMOS VLSI Design

    Stick Figure Construction  Draw horizontal wires as follows

    – Metal1 (blue) for Vdd on top – Metal1 (blue) for gnd at bottom – Diffusion for ptype just below Vdd – Alternative: use green with a yellow box – Diffusion for ntype just above Gnd – Metal2 for longer range wires

     Draw vertical poly for each gate input  Select which input corresponds to each vertical

    – “Euler’s Algorithm” later on will tell us this  Determine how/where to wire

    – Connections to Vdd/gnd – Connections from p to n types

     With “luck” you don’t have to “break” the diffusion  Key parameter to estimate from this: How “wide” is circuit? Layout Slide 9

    or X

    CMOS VLSI DesignLayout Slide 10

    Stick Diagrams

     Stick diagrams help plan layout quickly – Need not be to scale – Draw with color pencils or dry-erase markers – Relative position of key components

    What type of gates are these?

    What are the widths of the nmos and pmos transistors?

  • 6

    CMOS VLSI Design

    Alternative Invertor Circuit Layouts (Single Well)

    Layout Slide 11

    Vdd X Vdd

    X X X

    A X Y A X Y

    X X X

    Gnd Gnd X

    (Ignore Substrate Taps for Now)

    CMOS VLSI DesignLayout Slide 12

    Repetitive Custom Layout of Ring Oscillator

    Vdd

    X X X X X X

    X X X X X

    X X X X X X

    Gnd

    X X

  • 7

    CMOS VLSI Design

    Standardizing the Invertor

     Standard Height  Vdd and Ground match up  I/O Come down from M2 to

    Wiring Bays below cell  Width can vary

    Layout Slide 13

    Vdd

    Gnd

    In Out

    CMOS VLSI DesignLayout Slide 14

    Standard Cell Layout of Ring Oscillator

  • 8

    CMOS VLSI DesignLayout Slide 15

    Aside: Optimized Custom Layout of Ring Oscillator

    Vdd

    X X X X X

    X X

    X X X X

    X X X X X

    Gnd

    X X

    Note internal wiring

    CMOS VLSI DesignLayout Slide 16

    Complex Circuit Layouts

    Single diffusion runs Multiple Diffusion runs

    C (A+B) + AB

    Can you draw the transistor diagram?

  • 9

    CMOS VLSI Design

    Standard Cell Layout

    Layout Slide 17

    CMOS VLSI DesignLayout Slide 18

    Gate Layout  Standard cell design methodology

    – VDD and GND should be some standard height & parallel – Within cell, all pMOS in top half and all nMOS in bottom half – Preferred practice: diffusion for all transistors in a row

    • With poly vertical – All gates include well and substrate contacts

     Multi-gate circuits constructed by “snapping” gates together – If two standard cells abut, Vdd & GND “snap together” – Adjacent gates must still satisfy design rules at boundaries

     Bigger circuits constructed by rows of such multi-gates – With “routing channels” between them for wiring

    • Typically using 2 levels of metal – And “flips” to align Vdd and Gnd

  • 10

    CMOS VLSI Design

    Standard Cell Layout

    Layout Slide 19

    St an

    da rd

    H ei

    gh t

    Variable Width

    Bus connects to neighboring cells

    Bus connects to neighboring cells

    Well connects to neighboring cells

    Well connects to neighboring cellsp wellp well

    n well

    VDD Bus

    VSS Bus

    pmos transistors

    nmos transistors

    Internal Gate Wiring And Gate I/O contacts

    Audience Question: Why is “connecting to neighbors” a good thing?

    CMOS VLSI DesignLayout Slide 20

    Inverter Layout

    In Out

    preferred

    NOT to scale!

    What is the width of the nmos and pmos transistors? Why? What happens to size of inverter if we want to change widths?

  • 11

    CMOS VLSI DesignLayout Slide 21

    NAND Gate Layouts

    A

    B

    Out

    A B

    N

    preferred

    Audience Questions: • What is preferred width of pMOS? • Why is rightmost preferred?

    CMOS VLSI Design

    Inside A Modern “Standard Cell”

     Have Diffusion running horizontally – P type “below” the Vdd bus – N type “above” the GND

     Have Poly running vertically  Use metal to appropriately wire

    diffusions – To Vdd & GND – To the other diffusion – To different points in current

    diffusion  Attach I/O contacts to metal

    Layout Slide 22

    p wellp well

    n well

    VDD Bus

    VSS Bus

    pmos transistors

    nmos transistors

    Internal Gate Wiring And Gate I/O contacts

    Question to be answered by later “Euler Path” algorithm: Can we draw diffusion as single long rectangles without gaps?

  • 12

    CMOS VLSI Design

    A Simple Standard Cell Library

    Layout Slide 23

    CMOS VLSI Design

    More Complex Gates

    Layout Slide 24

  • 13

    CMOS VLSI Design

    Pitch-Matching (Fig. 1.65) Would it help if:  A could be slightly

    shorter?

     C could be slightly narrower?

     D could be smaller?

    Layout Slide 25

    CMOS VLSI Design

    What If We Want to “Stack” Gates?

    Layout Slide 26

    Vdd

    Gnd

    Vdd

    Gnd

    Gnd

    Vdd Design Rule says what?

    Vdd

    Gnd

    Vdd

    GndGnd

    Vdd

    But What if We “Flip” One Row?

  • 14

    CMOS VLSI Design

    MIPS ALU & Data Flow via Standard Cells

    Slide 27Layout

    CMOS VLSI Design

    Now for the Full 8 Bit Data Flow

    Layout Slide 28

  • 15

    CMOS VLSI Design

    What If We Can’t Use the Internal Wiring Channels?

    Layout Slide 29

    Audience Questions: 1. How many levels of metal do we need for this? 2. How would you estimate the height of the wiring channels? 3. Why is deciding which logic gate standard cell goes where important?

    Wiring Channel

    Wiring Channel

    CMOS VLSI Design

    A Fully Synthesized 8-bit MIPS

    Layout Slide 30