CMOS Transistor Scaling Past 32nmCMOS Transistor …download.intel.com/pressroom/pdf/kkuhn/Kuhn_Advanced_Semicondu… · CMOS Transistor Scaling Past 32nmCMOS Transistor Scaling Past

CMOS Transistor Scaling Past 32nmCMOS Transistor Scaling Past 32nm and

I li i V i iImplications on Variation

Kelin J. KuhnIntel Fellow

Director of Advanced Device TechnologyPortland Technology Development

Intel CorporationIntel Corporation

Kelin Kuhn / ASMC / SFO 2010 1

AGENDA

I. Overview – variation sourcesII. Next generation variation – lithographyIII. Next generation variation – polishg pIV. Next generation devicesV Measurements results and interpretationV. Measurements, results and interpretationVI. Closing thoughts


AGENDA



VARIATION SOURCESSOURCES

ContactContact

GateSpacer

Epi RSD


VARIATION SOURCES

STI PolishLER/LWR

OPC

SOURCES Poly

Kuhn ICCV 2009Kuhn ITJ 2009

Kuhn ICCV 2009

Gate granularityGate polish

Gate granularity

GateSpacer

Ranade IEDM 2005

StrainSteigerwald IEDM 2008

Oxide2 1 "Clean" CV @ 1MHz

RDF + implants

1.3

1.5

1.7

1.9

2.1

S C

apac

itanc

e [p

F]

Clean CV @ 1MHz

CV with Traps @ 1MHz

Kelin Kuhn / ASMC / SFO 2010 6Auth, VLSI 2008

0.7

0.9

1.1

-2 -1.5 -1 -0.5 0 0.5 1 1.5PMOS V-Gate [V]

PMO

S

C. PrasadKuhn iEDM 2007

AGENDA



Phase mask Phase mask data

Design

OPC/RET Trim mask Reticle

manufacturingTrim mask data

ExposurePutting it all

together for the gate layer of a

65nm MPU

Etch(magnified 25,000X)

Kelin Kuhn / ASMC / SFO 2010 8C. KenyonTOK conf.Dec. 2008


Design





65nm MPU



Layout Restrictions 65nm to 32nm65 nm Layout Style 32 nm Layout Style

• Bi directional features • Uni directional features• Bi-directional features• Varied gate dimensions• Varied pitches

• Uni-directional features• Uniform gate dimension• Gridded layout

Kelin Kuhn / ASMC / SFO 2010 10M. Bohr, ISCC, 2009


Design





65nm MPU



Optical Proximity Correction (OPC)As a Resolution Enhancement TechniqueAs a Resolution Enhancement Technique

Contour prediction – no OPC Contour prediction – with OPC

SEM Image – no OPC SEM Image – with OPC

Kelin Kuhn / ASMC / SFO 2010 12K. Wells-Kilpatrick: 2007

45nm: OPC as a Variation Management Technique

Top-down resist CD meets spec, but poor contrast leads to poor resist profile which gets transferred to metal pattern after etch, resulting in shorting marginality

Kelin Kuhn / ASMC / SFO 2010 13Computational lithography solutionK. Kuhn, IEDM 2007


Design





65nm MPU



MEEF Mask Error Enhancement Factor

• MEEF is a scaling factor that causes certain layout• MEEF is a scaling factor that causes certain layout geometries to exhibit a greater sensitivity to mask dimension tolerances.

• Any dimensional error in the mask is magnified on the wafer by the MEEF value.

Wwafer= MEEF * Wmask

• Depending on the value of the mask error and the lithography exposure/focus conditions the final printedlithography exposure/focus conditions the final printed pattern can be either larger or smaller.


MEEF Impact on Ze Errorp

Ze error can be eitherpositive or negative 65nm Simulation Notch width 120nmpositive or negative 65nm Simulation Notch width = 120nm

Notch height = 250nm

MEEF = 8.4

YellowYellow: DCCD contour after OPCGreen: with -3.375 nm mask making errorR d ith 3 375 k ki


Red: with 3.375 nm mask making error

MEEF and Historical gate CD vs. pitch1262 CD vs. Pitch

90

100

110

120

nm)

nm)

90nm node 1264 PSM CD vs. Pitch

70

80

90

nm)

nm)

65nm node1260 CD vs. Pitch

140

150

160

170

nm)

(nm

)

130nm node

50

60

70

80

100 200 300 400 500 600 700 800 900 1000

CD

(nC

D (n

30

40

50

60

100 200 300 400 500 600

CD

(nC

D (n

100

110

120

130

200 300 400 500 600 700 800 900 1000

CD

(C

D (

Pitch (nm)100 200 300 400 500 600

Pitch (nm)

45nm node

Pitch (nm)

1268 PSM CD vs Pitch32nm node

193nm; APSM; model-based OPC

248nm; OAI; model-based OPC

193nm; OAI; model-based OPC

(nm

)D

(nm

)

45nm node

Contacted

1268 PSM CD vs. Pitch

55

60

65

70

(nm

)

32nm node

D (n

m)

50 100 150 200 250 300 350 400

CD

CD gate pitch

40

45

50

55

80 100 120 140 160 180

CD

C

D

C Kenyon Pitch (nm) Pitch (nm)

193nm; APSM; model- based OPCdouble patterning

193nm; immersion; APSM; model- based OPC; double patterning; polarization

C. KenyonTOK conf.Dec. 2008


Low MEEF requires targeting in the “flat” portion of CD vs. pitch Process innovations continue this trend in the 32nm node


Design





65nm MPU



FLARE• Flare is unwanted scattered

light arriving at the wafer• Flare is caused by

interactions that force theinteractions that force the light to travel in a "non-ray trace" direction.

• Flare is both a function of local environment around a feature (short range flare)feature (short range flare) and the total amount of energy going through the gy g g glens (long range flare).


Impact of flare on gate CDs All structures have identical reticle CD and pitch

73

74High chrome density

DC

CD

69

70

71

72

m)

1x09

0a D

66

67

68

69

CD

(nm

Moderate chrome density

63

64

65

DV Near Etest E-Test FREA Nested DV Nested Metro

1nm

• During 65nm process development, large CD d i ti b d f t t h i

chrome density

Low chrome density

Structure

deviations were observed for structures having identical pitch and reticle CD due to flare

• Gates only 500m away from one another could C. KenyonTOK conf.Dec. 2008


be >5nm different in CD

Flare Variation Improvement with OPCwith OPC

56.0 – 63.0

49 0 56 0

Color Code

Chrome Fraction56.0 – 63.0

49 0 56 0

Color Code

Chrome Fraction

49.0 - 56.0

42.0 – 49.0

35.0 – 42.0

28.0 – 35.0

49.0 - 56.0

42.0 – 49.0

35.0 – 42.0

28.0 – 35.0

21.0 – 28.0

14.0 – 21.0

7.0 – 14.0

21.0 – 28.0

14.0 – 21.0

7.0 – 14.0

0.0 – 7.00.0 – 7.0

Development effort produced an algorithm capable of scanning designs and binning regions by local chrome fraction

Binning algorithm is combined with flare-calibrated OPC model


g a go t s co b ed t a e ca b ated O C odeC. Kenyon, TOK conf., Dec. 2008


Design





65nm MPU



45nm highlights role of lithography/etch in resolving LER/LWRresolving LER/LWR

Improvement A

Original Final after improvements A,B,C

Improvements B,C

Kelin Kuhn / ASMC / SFO 2010 23K. Kuhn, ITJ, 2008

Technology Trend Systematic Gate CD Lithography Variation

Gate CD variation improvements10

30nm

Systematic Gate CD Lithography Variation

Gate CD variation improvements with technology scaling

lized

to 1

3

0 7X1

on n

orm

a

WID-total0.7X

G (V

aria

tio

WIW-total TOTAL

0.1130nm

33690nm260

65nm220

45nm160

32nm112 5

LOG

GENERATIONGATE PITCH336 260 220 160 112.5

Critical to management of variation is the ability to deliver a 0.7X gate CD variation improvement in each generation

GATE PITCH

Kelin Kuhn / ASMC / SFO 2010 24enabled by continuous process technology improvements

Lithography Pipeline1 1000

W l th

N

Wavelength248nm

193nm

TER

0.1

MIC

RO

N

100OPCPhase shiftImmersion A

NO

MET

32nm22nm

15nmFeature Size EUV

13.5nm

NA

0.011980 1990 2000 2010 2020

1015nm

Extend 193nm Optical Lithography as far as possibleDeploy EUV Lithography when available/affordable


p y g p y

Non-EUV Lithography Beyond 32 nmPitch Doubling 2-D Features

Double PatterningDouble Patterning• Pitch doubling

• Improved 2-D features• Improved 2-D features

Spacer Gate Patterning• Pitch doubling

• Improved variation


M. Bohr, ISCC, 2009Bencher et al, Proc. of SPIE Vol. 6924 69244E-7

Pitch doubling and gate CD control

Pattern transfer layer 2nd pattern transfer layer1st pattern transfer layer Neither Resist Freeze

Gate layerPattern transfer layer

Gate layer2 pattern transfer layer

nor Double Pattern Transfer achieve full benefit of patterningbenefit of patterning at ½ pitch

Both techniques still i l tirequire resolution

of a very small space (MEEF LWR etc )

Resist freeze

(MEEF, LWR etc.)

Double PatternT f


TransferC. Kenyon, TOK conf., Dec. 2008

Disadvantages of Double-patterningMisalignment

DSA

TA

LZED

IDN

OR

MA

Print 1 Print 2Registration (nm)

Misalignment between the 2 exposures is a crucial liability for this technique and can limit its usability

Transistor parameters can be affected by asymmetry between the source and drain regions


Pitch doubling and gate CD matching

in

A AA1266

12641262

860

M V

ccm

i

B B BB1266

SRA

M

Gate CD mismatch

Pitch doubling eliminates the close correlation which currently exists between the CDs of adjacent gates

Thi h i li ti f ll d th i itThis has implications for memory cells and other circuits which depend upon this CD matching

Kelin Kuhn / ASMC / SFO 2010 29C. Kenyon, TOK conf., Dec. 2008

Pitch doubling and gate CD matching

Pitch doublingadjacent gate CDadjacent gate CD

mismatches

Total gate CD di t ib tidistribution

Single patterning adjacent gate CDadjacent gate CD mismatches

Single patterning: the distribution of CD mismatches between dj t t i ll f ti f t t l t CD i ti

-4 -3 -2 -1 0 1 2 3 4

adjacent gates is a very small fraction of total gate CD variation

Pitch doubling: the distribution of CD mismatches is GREATER than the total gate CD variation


GREATER than the total gate CD variationC. Kenyon, TOK conf., Dec. 2008

Non-EUV Lithography Beyond 32 nmPitch Doubling 2-D Features

Double PatterningDouble Patterning• Pitch doubling

• Improved 2-D features• Improved 2-D features

Spacer Gate Patterning• Pitch doubling

• Improved variation

Kelin Kuhn / ASMC / SFO 2010 31M. Bohr, ISCC, 2009Bencher et al, Proc. of SPIE Vol. 6924 69244E-7

Alternative: Spacer patterningp p g

Spacer patterning retains correlation between doubled features

Kelin Kuhn / ASMC / SFO 2010 32Bencher et al, Patterning by CVD Spacer Self Alignment DoublePatterning (SADP), Proc. of SPIE Vol. 6924 69244E-7

Alternative: Spacer patterningp p g

Potential asymmetriesPotential asymmetries

Need for trim mask

Cross-section Top-down

However spacer patterning comes with challenges of its own

Kelin Kuhn / ASMC / SFO 2010 33Bencher et al, Patterning by CVD Spacer Self Alignment DoublePatterning (SADP), Proc. of SPIE Vol. 6924 69244E-7

AGENDA



HiK-MG: Gate First vs Gate LastGate-First

Dep Hi-k & Met 1

Patt Met 1 & Dep Met 2

Patt Met 2 & Etch Gates

S/D formation & Contacts

Dep & PattHik+Gate

S/D formation &ILD dep /polish

Rem Gate & Patt Met 1

Dep Met 2+Fill &Polish

Hik-First, Gate-Last

Advantages of gate last flow• High Thermal budget available for Midsection

– Better Activation of S/D ImplantsBetter Activation of S/D Implants• Low thermal budget for Metal Gate

– Large range of Gate Materials available• Significant enhancement of strain

Kelin Kuhn / ASMC / SFO 2010

Significant enhancement of strain– Both NMOS and PMOS benefit

Auth – Intel – VLSI 2008 35

CMP Integration at 45 nm – HiK Metal Gate

STI deposition and polish STI STI Wells and VT implants

ALD deposition of high-k gate dielectric

Polysilicon deposition and gate patterning

CMPCMP

POP POP CMPCMPPolysilicon deposition and gate patterning

S/D extensions, spacer, Si recess and SiGe deposition

S/D formation, Ni silicidation, ILD0 deposition

CMPCMP

Poly Opening Polish, Poly removal

PMOS workfunction metal deposition

Metal gate patterning NMOS WF metal deposition

K.Mistry et al., IEDM (2007)C A th t l VLSI S (2008)

Metal gate patterning, NMOS WF metal deposition

Metal gate fill and polish, ESL deposition MGD MGD CMPCMP

First Generation HiK Replacement Metal Gate

C.Auth et al. VLSI Symp, (2008)J. Steigerwald, IEDM (2008)J. Steigerwald, IEDM (2008)


First Generation HiK – Replacement Metal GateThree critical CMP operations in the FE




Polysilicon deposition and gate patterningPOP POP CMPCMP

CMPCMP




CMPCMP











STR Pattern Density Variation Impacty p

High Pattern Density Low Pattern DensityHigh Pattern Density Low Pattern Density

OxideSiliNitride

OxideSilicon

Slower Polish Rate Faster Polish Rate


STI Step Height VariationHigh PatternDensity Area

Low PatternDensity Area

STI topography

STI STItopography

impacts transistorLe and Ze

Positive Step Height Zero Step Height


STI Step Height VariationHigh PatternDensity Area

Low PatternDensity Area

STI t hSTI STI

STI topographyimpacts transistorLe and Ze

Poly Poly

Zero Step Height


STI Step Height Impact on Gate CD

NegativeSTI

Polyg

Step Height GATE

Diffusion

“Dogbone” Lg is longer at the diffusion boundary

PositiveSTI

PolyStep Height GATE

Diffusion

“Icicle” Gate CD is shorter at the diffusion boundary


Gate CD is shorter at the diffusion boundary





CMPCMP

POP POP CMPCMPPolysilicon deposition and gate patterning



CMPCMP











Variation Challenges of RMG CMP Steps• Gate height control critical to reducing variation• PMOS/NMOS differences complicate CMPp

nWFM pWFM

NiSi

HiK

NMOS PMOS

Epi S/DHiK

NMOS PMOS

C.Auth et al. VLSI Symp, (2008)

Kelin Kuhn / ASMC / SFO 2010 43J. Steigerwald, IEDM 2008

Variation Challenges of RMG CMP StepsOVERPOLISHExposes raised S/D

UNDERPOLISHUnderetched contact

NMOS S/D

Rext/mobility impact Rext impact

Gate region

region contact

S/D region – attacked during poly etch

S/D region – marginal contact


during poly etchJ. Steigerwald, IEDM 2008

contact

45 nm: POP CMP ImprovementOverscaling Topography ImprovementOverscaling Topography Improvement

1ra

phy 0.7X

improvement

Topo

g

0.1 45nm: 2X greater than

standard

CM

P

0 01

standard technology

scaleJ. Steigerwald, IEDM 2008

Technology node (nm)

0.01350 250 180 130 90 65 45

Improvements in polish enabled dramatic impro ements in topograph ariation

Technology node (nm)


improvements in topography variation

Generational ImprovementsPatterning and Polish

45nm – WIDE32nm – WIDE

0 171 m2

22nm – WIDE0.092 m2

90nm – TALL1.0 m2

65nm – WIDE - 0.57 m245nm WIDE

0.346 m2 0.171 m2

65nm to 22nm: Patterning and polish enhancements

• Improved CD uniformity across STI boundaries• Square corners (eliminate “dogbone” and “icicle” corners)


AGENDA



MOSFET Ch llChallenges

Capacitance (Increased fringe to

Gate control(SCE limitations ith ll L ff)

( gcontact/facet)Resistance

(Decreased S/D opening) Contact with smaller Leff)Contact

GateSpacer

Epi RSD

Mobility(Reduced strain with

decreased pitch)


decreased pitch)

NextG ti

MOSFET Ch llGeneration

Capacitance (Increased fringe to

Challenges

Gate control(SCE limitations ith ll L ff)

( gcontact/facet)Resistance

(Decreased S/D opening) Contact with smaller Leff)Contact

GateSpacer

Epi RSD

Mobility(Reduced strain with

decreased pitch)


decreased pitch)

Ultra-thin bodyith RSDwith RSD

Contact

SpacerGate

Epi RSD

Ultra-thinbody (UTB)


MuGFET

Contact

SpacerGate

Vertical thin body


MuGFET VARIANTS FINFET TRIGATE PI GATEFINFET TRIGATE PI GATEVARIANTS

Nearly ideal sub-th h ld lha

nnel

gate

FINFET TRIGATE PI-GATE

hann

el

gatehann

el

gate

FINFET TRIGATE PI-GATE

threshold slope (gates tied together)

BOX ch

Silicon

-GATE GAA (GATE-ALL-AROUND)

BOX ch

Silicon

BOX ch

Silicon

-GATE GAA (GATE-ALL-AROUND)


Nanowire

Contact

SpacerGate

Nanowire


Nanowire

ContactLooking at all these i d t il

SpacerGate

in more detail

Nanowire


Ultra-thin bodyith RSD

Benefitswith RSD

Extension of l t h lplanar technology

(less disruptive to manufacturing)

Improved RDF (low doped

channel)

C tibl

channel)

Compatible with RSD

technology

Excellent channel

Potential for body bias


controly

55

ChallengesUltra-thin bodyith RSD

V i ti

with RSDCapacitance

(Increased fringe to Variation:(film thickness changes affects

VT and DIBL)

(Increased fringe to contact/facet)

Rext: (Xj/Tsi

limitations)

VT and DIBL)

limitations)

Strain:(strain transfer from

Manufacturing:

(strain transfer from S/D into the channel) Performance:

(transport challenges with thin Tsi)


g(requires both thin Tsi and thin BOX)

with thin Tsi)

56

Ultra-thin bodyBarral – CEA-LETI– IEDM 2007

Ch IBM VLSI 2009Cheng – IBM – VLSI 2009

Lg=25nmTsi=6nm


MuGFET Benefits

Nearly ideal sub-th h ld l

Double-gate relaxes Tsi requirementsFin Wsi > UTB Tsi


(less scattering, improved VT shift)


channel)channel)

Excellent channel controlCan be on


controlCan be on bulk or SOI

58

MuGFET with RSD

Benefitswith RSD






channel)channel)

Compatible with RSD

technology

Excellent channel control


gy control

59

MuGFET Benefits

Possibility for i d d t t


independent gate operation



channel)channel)



control

60

MuGFET ChallengesVariation

(Mitigating RDF but acquiring Gate wraparound

(Endcap coverage)Capacitance Hsi/Wsi/epi) (Endcap coverage)Capacitance (fringe to contact/facet)(Plus, additional “dead

space” elements)

Small fin pitch

space elements)

Small fin pitch (2 generation scale?)

Fin/gate fidelity on 3’D(Patterning/etch)

Rext: (Xj/Wsi

Topology(Polish / etch challenges)

Fin Strain engr.(Effective strain

t f f fi


( jlimitations)

challenges)transfer from a fin into the channel)

61

MuGFETKavalieros – Intel – IEDM 2006

Chang – TSMC – IEDM 2009


Nanowire Benefits


Nanowire further


Nanowire further relaxes Tsi / Wsi

requirementsImproved RDF

(low doped channel)channel)



control

63

BenefitsNanowire


Nanowire further


Nanowire further relaxes Tsi / Wsi

requirementsImproved RDF

(low doped channel)channel)

Compatible with RSD

technology



gy control

64

Nanowire ChallengesGate conformality

Capacitance (fringe to contact/facet)

Gate conformality(dielectric and metal)

(Plus, additional “dead space” elements)

Integrated wire fabrication

Wire stability(bending/warping)

Variation(Mitigating RDF but

wire fabrication (Epitaxy? Other?)

(bending/warping)

acquiring a myriad of new sources)Mobility degradation

(scattering)

Fi / t fid lit 3’D

Rext:

Fin Strain engr.(Effective strain

transfer from wire

Fin/gate fidelity on 3’D(Patterning/etch)

Topology


(Xj/Wsi limitations)

into the channel)Topology

(Polish / etch challenges) 65

Nanowire FETsDupre – CEA-LETI – IEDM 2008

Bangsaruntip – IBM – IEDM 2009


AGENDA



Systematic and Random

• Statistician’s viewpoint:

Random

viewpoint:Systematic

• Process engineer’s viewpoint:

FixFixviewpoint:

Random Systematic

• Device engineer’s viewpoint:

VT1

D

VT2 VT1

D

VT2

p

Random Systematic

S D S D S D S D


Random Systematic

Measurement of Random and Systematic VT Variation at the Device LevelVT Variation at the Device Level

Traditional method:VT1 VT2 Traditional method: 1. Measure two identical adjacent devices and

extract the difference (VTA-VTB)2. Measure the entire population of all devices

VT1

S D

VT2

S D2. Measure the entire population of all devices

and extract (VTpop)

Random Variation for a matched pair

)()( DVTVTVTStdDevRandom BAmp

)()( DVTVTVTStdDRandom Variation for a single device 2

)(2

)( DVTVTVTStdDevRandom BAdeviceone

22

2)()(

DVTVTSystematic pop

Systematic Variation for a single device


2

Using Arrays for Variation Measurement(this example is metal resistors)

256 256

(this example is metal resistors)

1024

256structures

In low densityfillers

256structures

in highdensityfillers

Etest structuresin nominal density

fillers fillers

256Nom

256NomNom

densityfillers

Nomdensityfillers


Using Arrays for Variation Measurement(this example is metal resistors)(this example is metal resistors)

lowdensity

highdensity

nomdensity

nom nom


Using Arrays for Variation Measurement(this example is metal resistors)(this example is metal resistors)

lowdensity

highdensity

nomdensity

nom nom


Important of Comprehending de Biasing in Arraysde-Biasing in Arrays


Random and Systematic Variationfor Matched Ring Oscillatorsfor Matched Ring Oscillators

Random:• Calculate Delta 2

200*F BF AFreqBFreqADelta

Calculate Delta

• Random Variation

2FreqBFreqA

)(DeltaStdDevRand per data unit

)(FreqAStdDevSystematic:• Total Sigma per data unit

2)()( FreqBMeanFreqAMean

• Grand Mean2

22

100* RandSyst

• Systematic Variation per data unit

Total Variation: 100*)(FreqAStdDevTotal per data unit


Total Variation:)(FreqAMean per data unit

45nm Product wafer: Random variation

1 5iatio

n

15cm

1

1.5

ZED

% V

ari

8 cm

0

0.5

NO

RM

ALI

Z

K. Kuhn, ITJ 2008

Kelin Kuhn / ASMC / SFO 2010 75N

Standard oscillator

,

Random and Systematic Variation TrendsNormalized systematic variation

standard deviation per oscillator (%)

4

5

(%)

1

2

3

4

PE

RC

EN

T Systematic WIW variation is comparable from one generation to the next

0

1

130nm 90nm 65nm 45nm 32nm

P generation to the next

Normalized random variationstandard deviation per oscillator (%)

5

%)

Random WIW ariation in

2

34

ER

CE

NT

(% Random WIW variation in 32nm is comparable to 45nm and significantly

HiK-MG

01

130nm 90nm 65nm 45nm 32nm

PE improved over 65nm and

90nm due to HiK-MG


AGENDA



Yield: A pragmatic measure of variation

90 nm 65 nm 45 nm 32 nm350 nm 250 nm 180 nm 130 nm

og s

cale

)D

ensi

ty (l

oD

efec

t D

2002 2003 2004 2005 2006 2007 2008 2009 20101993 1994 1995 1996 1997 1998 1999 2000 2001


Yield: A pragmatic measure of variation

90 nm 65 nm 45 nm 32 nm90 nm 65 nm 45 nm 32 nm350 nm 250 nm 180 nm 130 nm

og s

cale

) 90 nm 65 nm 45 nm 32 nm

(log

scal

e)

Den

sity

(lo

Den

sity

(

Def

ect D

Def

ect

2002 2003 2004 2005 2006 2007 2008 2009 20101993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009

2002 2003 2004 2005 2006 2007 2008 2009


Closing ThoughtsClosing Thoughts

Process variation is not anProcess variation is not an insurmountable barrier to Moore’s

L b t i i l thLaw, but is simply another challenge to be overcome.g


Q&AQ&AQ&AQ&A


Documents

CMOS Transistor Scaling Past 32nmCMOS Transistor …download.intel.com/pressroom/pdf/kkuhn/Kuhn_Advanced_Semicondu… · CMOS Transistor Scaling Past 32nmCMOS Transistor Scaling Past