Click here to load reader

Transistor Theory and DC Characteristics - · PDF file4: Nonideal Transistor Theory CMOS VLSI DesignCMOS VLSI Design 4th Ed. 28 Ideal vs. Simulated nMOS I-V Plot 65 nm IBM process,

  • View
    226

  • Download
    0

Embed Size (px)

Text of Transistor Theory and DC Characteristics - · PDF file4: Nonideal Transistor Theory CMOS VLSI...

  • Dr. Bassam Jamil

    Adopted from slides of the

    textbook

    Transistor Theory

    and

    DC Characteristics

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 2

    Outline

    Transistor Theory

    Channel Formation and operation Regions

    I-V Characteristics

    C-V Characteristics

    Gate and Diffusion Capacitance

    Nonideal characteristics

    DC Response

    DC Response

    Logic Levels and Noise Margins

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 3

    Introduction

    So far, we have treated transistors as ideal switches

    An ON transistor passes a finite amount of current

    Depends on terminal voltages

    Derive current-voltage (I-V) relationships

    Transistor gate, source, drain all have capacitance

    I = C (DV/Dt) -> Dt = (C/I) DV

    Capacitance and current determine speed

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 4

    polysilicon gate

    (a)

    silicon dioxide insulator

    p-type body+-

    Vg < 0

    MOS Device Channel Formation

    Gate and body form MOS

    capacitor

    Operating modes

    Accumulation

    Depletion

    Inversion

    (b)

    +-

    0 < Vg < Vt

    depletion region

    (c)

    +-

    Vg > Vt

    depletion region

    inversion region

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 5

    Terminal Voltages

    Mode of operation depends on Vg, Vd, Vs

    Vgs = Vg Vs

    Vgd = Vg Vd

    Vds = Vd Vs = Vgs - Vgd

    Source and drain are symmetric diffusion terminals

    By convention, source is terminal at lower voltage

    Hence Vds 0

    nMOS body is grounded. First assume source is 0 too.

    Three regions of operation

    Cutoff

    Linear

    Saturation

    Vg

    Vs

    Vd

    Vgd

    Vgs

    Vds

    +-

    +

    -

    +

    -

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 6

    nMOS Cutoff

    No channel

    Ids 0

    +-

    Vgs

    = 0

    n+ n+

    +-

    Vgd

    p-type body

    b

    g

    s d

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 7

    nMOS Linear

    Channel forms

    Current flows from d to s

    e- from s to d

    Ids increases with Vds

    Similar to linear resistor

    +-

    Vgs

    > Vt

    n+ n+

    +-

    Vgd

    = Vgs

    +-

    Vgs

    > Vt

    n+ n+

    +-

    Vgs

    > Vgd

    > Vt

    Vds

    = 0

    0 < Vds

    < Vgs

    -Vt

    p-type body

    p-type body

    b

    g

    s d

    b

    g

    s dIds

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 8

    nMOS Saturation

    Channel pinches off

    Ids independent of Vds

    We say current saturates

    Similar to current source

    +-

    Vgs

    > Vt

    n+ n+

    +-

    Vgd

    < Vt

    Vds

    > Vgs

    -Vt

    p-type body

    b

    g

    s d Ids

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 9

    I-V Characteristics

    In Linear region, Ids depends on

    How much charge is in the channel?

    How fast is the charge moving?

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 10

    Long Channel I-V

    MOS structure looks like parallel plate capacitor

    while operating in inversions

    Gate oxide channel

    Qchannel = CV

    C = Cg = eoxWL/tox = CoxWL

    V = Vgc Vt = (Vgs Vds/2) Vt

    n+ n+

    p-type body

    +

    Vgd

    gate

    + +

    source

    -

    Vgs

    -drain

    Vds

    channel-

    Vg

    Vs

    Vd

    Cg

    n+ n+

    p-type body

    W

    L

    tox

    SiO2 gate oxide

    (good insulator, eox

    = 3.9)

    polysilicon

    gate

    Cox = eox / tox

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    Long Channel I-V

    3: CMOS Transistor Theory 11

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 12

    nMOS Saturation I-V

    If Vgd < Vt, channel pinches off near drain

    When Vds > Vdsat = Vgs Vt

    Now drain voltage no longer increases current

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 13

    nMOS I-V Summary

    2

    cutoff

    linear

    saturatio

    0

    2

    2n

    gs t

    dsds gs t ds ds dsat

    gs t ds dsat

    V V

    VI V V V V V

    V V V V

    Shockley 1st order transistor models

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 14

    Example

    The following is a 0.6 mm process:

    tox = 100

    m = 350 cm2/V*s

    Vt = 0.7 V

    Plot Ids vs. Vds

    Vgs = 0, 1, 2, 3, 4, 5

    Use W/L = 4/2 l

    14

    2

    8

    3.9 8.85 10350 120 A/V

    100 10ox

    W W WC

    L L L m

    0 1 2 3 4 50

    0.5

    1

    1.5

    2

    2.5

    Vds

    I ds (m

    A)

    Vgs

    = 5

    Vgs

    = 4

    Vgs

    = 3

    Vgs

    = 2

    Vgs

    = 1

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    Another Example

    3: CMOS Transistor Theory 15

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 16

    pMOS I-V

    All dopings and voltages are inverted for pMOS

    Source is the more positive terminal

    Mobility mp is determined by holes

    Typically 2-3x lower than that of electrons mn

    120 cm2/Vs in AMI 0.6 mm process

    Thus pMOS must be wider to

    provide same current

    In this class, assume

    mn / mp = 2

    -5 -4 -3 -2 -1 0-0.8

    -0.6

    -0.4

    -0.2

    0

    I ds(m

    A)

    Vgs

    = -5

    Vgs

    = -4

    Vgs

    = -3

    Vgs

    = -2

    Vgs

    = -1

    Vds

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 17

    Reverse

    Voltages

    Terminals

    Change > to <

    Positives to negatives

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 18

    Capacitance

    Any two conductors separated by an insulator have

    capacitance

    Gate to channel capacitor is very important

    Creates channel charge necessary for operation

    Source and drain have capacitance to body

    Across reverse-biased diodes

    Called diffusion capacitance because it is

    associated with source/drain diffusion

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    MOS Device Capacitances

    3: CMOS Transistor Theory 19

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 20

    Gate Capacitance

    Approximate channel as connected to source

    Cgs = eoxWL/tox = CoxWL = CpermicronW

    Cpermicron is typically about 2 fF/mm

    n+ n+

    p-type body

    W

    L

    tox

    SiO2 gate oxide

    (good insulator, eox

    = 3.9e0)

    polysilicon

    gate

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    Gate Overlap Capacitance

    3: CMOS Transistor Theory 21

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    Approximation of Intrinsic Gate Capacitance

    3: CMOS Transistor Theory 22

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory 23

    Diffusion Capacitance

    Csb, Cdb

    Undesirable, called parasitic capacitance

    Capacitance depends on area and perimeter

    Use small diffusion nodes

    Comparable to Cg

    for contacted diff

    Cg for uncontacted

    Varies with process

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    Diffusion Cap Calculations

    Total source diff capacitance

    Source area (AS) = W D

    Source Perimeter (PS) = W + 2D

    3: CMOS Transistor Theory 24

    * The side wall capacitance

    abutting the channel is:

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    Diffusion Cap Example

    3: CMOS Transistor Theory 25

    l = 25 nm

    W = 4 l = 0.1mm

    D = 5 l = 0.125mm

  • CMOS VLSI Design CMOS VLSI Design 4th Ed.

    Nonideal

    Transistor

    Theory

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 27

    Outline

    Nonideal Transistor Behavior

    High Field Effects

    Mobility Degradation

    Velocity Saturation

    Channel Length Modulation

    Threshold Voltage Effects

    Body Effect

    Drain-Induced Barrier Lowering

    Short Channel Effect

    Leakage

    Subthreshold Leakage

    Gate Leakage

    Junction Leakage

    Process and Environmental Variations

  • CMOS VLSI Design CMOS VLSI Design 4th Ed. 4: Nonideal Transistor Theory 28

    Ideal vs. Simulated nMOS I-V Plot

    65 nm IBM process, VDD = 1.0 V

    This is due to:

    Velocity Saturation

    Mobility depredation

    0 0.2 0.4 0.6 0.8 1

    0

    200

    400

    600

    800

    1000

    1200

    Vds

    Ids (mA)

    Vgs = 1.0

    Vgs = 1.0

    Vgs = 0.8

    Vgs = 0.6

    Vgs = 0.4

    Vgs = 0.8

    Vgs = 0.6

    Channel length modulation:

    Saturation current increases

    with Vds

    Ion = 747 mA @

    Vgs = Vds = VDD

    Simulated

    Ideal

    Velocity saturation & Mobility degradation:

Search related