VLSI, MOS Transistor, GTU

Gujarat Technological University Subject: VLSI Technology & Design Code:2161101 Topic_2_Fabrication of MOSFET

Compiled By: Prof G B RathodBVM Engineering CollegeET DepartmentV V Nagar-Gujarat-India-388120Email: [email protected]

Gujarat Technological UniversitySubject: VLSI Technology & DesignCode:2161101Topic_3_MOS Transistor

OutlinesThe Metal Oxide Semiconductor (MOS) structure The MOS System under external bias Structure and Operation of MOS transistor MOSFET Current-Voltage characteristics MOSFET scaling and small-geometry effects MOSFET capacitances OutcomesReferences

23-Feb-16BVM ET2

The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET3Compare to BJT, MOS transistor occupies a relatively smaller silicon area, and its fabrication used to involve fewer processing steps.We will examine the basic structure and electrical behavior of nMOS as well as pMOS devices. The basic operation principles of both nMOS and pMOS transistor are very similar to each other.We will start with the electrical behavior of the simple two terminal MOS structure shown in figure.3.1Note that, the structure consist of three layers:

The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET4

The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET5Three layers are: The metal gate electrode, the insulating oxide(SiO2) layer, and the p-type bulk semiconductor, called the substrate.As such , the MOS structure forms a capacitor, with the gate and the substrate acting as the two terminals and oxide layer as the dielectric. The equilibrium concentrations of mobile carriers in a semiconductor always obey the Mass Action Law given by

The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET6Here, n and p denote the mobile carrier concentrations of electrons and holes, respectively, and ni denotes the intrinsic carrier concentration of silicon, which is function of Temerature T. (300K)

Assuming that the substrate is uniformly doped with acceptor(e.g. Boron concentration NA, the equilibrium electron and hole concentrations in the p-type substrate are approx given by eqn 3.2


The doping concentration of NA is typically on the order of 10^15 to 10^16 cm^-3; thus , it is much greater than the intrinsic carrier concentration ni.

The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET8The energy band diagram of p-type substrate is shown in fig 3.2. The band gab between the conduction band and the valence band for silicon is approximately 1.1 eV.The location of the equilibrium Fermi level EF with in the band gap is determined by the doping type and the doping concentration in the silicon substrate.The Fermi potential , which is a function of temperature and doping, demotes the difference between the intrinsic Fermi level Ei and the Fermi level EF.



For a p-type semiconductor, Fermi potential can be approximated by

Whereas for an n-type semiconductor(doped with donor concentration ND), the Fermi potential is given by


Here, k denotes the Boltzmann constant an q denotes the unit charge.Note that the definition given in (3.4) and (3.5) results in a positive Fermi potential for n-type material, and a negative Fermi potential for p-type material. The electron affinity of silicon, which is the potential difference between the conduction band level and the vacuum(free space) level, is denoted by qX in fig. 3.2.

The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET12The energy required for an electron to move from the Fermi level into free space is called the work function, and is given by ,

The insulating silicon dioxide layer between the silicon substrate and the gate has a large band gap of about 8 eV and an electron affinity of about 0.95 eV. On the other hand, the work function of an aluminum gate is about 4.1 eV.Figure 3.3 shows the energy band diagram of three layers.


The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET14Now consider that the three components of the ideal MOS system are brought into physical contact.The Fermi levels of all three materials must line up, as they form the MOS capacitor as shown in figure 3.1.Because of the work-function difference between the metal and the semiconductor, a voltage drop occurs across the MOS system.Part of this built in voltage drop occurs at the silicon surface next to the silicon oxide interface, forcing the energy bands of silicon to bend in this region.


The Metal Oxide Semiconductor (MOS) structure23-Feb-16BVM ET16The resulting combine energy band diagram of the MOS system is shown in fig.3.4.Notice that the equilibrium Fermi levels of the semiconductor Si substrate and the metal gate are at the same potential. The bulk Fermi level is not significantly affected by the band bending, whereas the surface Fermi level moves closer to the intrinsic Fermi (mid-gap) level.The Fermi potential at the surface, also called surface potential , is smaller in magnitude than the bulk Fermi potential.

The MOS System under External Bias23-Feb-16BVM ET17We now turn our attention to the electric behavior of the MOS structure under externally applied bias voltage.Assume that the substrate voltage is set at VB=0, and let the gate voltage be the controlling parameter.Depending on the polarity and the magnitude of VG, three different operating regions can be observed for the MOS system: accumulation, depletion and inversion.If a negative voltage VG is applied to the gate electrode, the holes in the p-type substrate are attracted to the semiconductor-oxide interface.

The MOS System under External Bias23-Feb-16BVM ET18

The MOS System under External Bias23-Feb-16BVM ET19The majority carrier concentration near the surface becomes larger than the equilibrium hole concentration in the substrate; hence this condition is called carrier accumulation on the surface.( Fig. 3.5).Note that in this case, the oxide electric field is directed towards the gate electrode. The negative surface potential also causes the energy bands to bend upward near the surface.While the hole density near the surface increases as a result of the applied negative gate bias, the electron(minority carrier) concentration decreases as the negative charged electrons are pushed deeper into the substrate.

The MOS System under External Bias23-Feb-16BVM ET20Now consider the next case in which a small positive gate bias VG is applied to the gate electrode.Since the substrate bias is zero, the oxide electric field will be directed towards the substrate in this case.The positive surface potential causes the energy bands to bend downward near the surface, as shown in figure 3.6.The majority carriers, i.e., the holes in the substrate, will be repelled back into the substrate as a result of the positive gate bias, and these holes will leave negatively charged fixed acceptor ions behind.Thus , a depletion region created near the surface.


The MOS System under External Bias23-Feb-16BVM ET22The thickness of depletion region on the surface can easily found as a function of the surface potential. Assume that the mobile hole charge in a thin horizontal layer parallel to the surface is

The change in surface potential require to displace this charge sheet dQ by distance Xd away from the surface can be found by using the Poisson equation.


Integrating (3.7) along the vertical dimension (perpendicular to the surface ) yields


Thus, the depth of the depletion region is

The MOS System under External Bias23-Feb-16BVM ET25And the depletion region charge density, which consists solely of fixed acceptor ions in this region, is given by the following expression

The amount of this depletion region charge plays a very important role in the analysis of threshold voltage.Now , when we increase the positive gate bias. As a result of the increasing surface potential, the downward bending of the energy bands will increase as well.


The MOS System under External Bias23-Feb-16BVM ET27Eventually, the mid-gap energy level Ei becomes smaller than the fermi level on the surface, which means that the substrate semiconductor in this region become n-type.Within this thin layer, the electron density is larger than the majority hole density, since the positive gate potential attracts additional minority carriers(electrons) from the bulk substrate to the surface(fig.3.7).The n-type region created near the surface by positive gate bias is called the inversion layer, and this condition is called surface inversion.It will be seen that the thin inversion layer on the surface with a large mobile electron concentration can be utilized for conducting current between two terminals of the MOS transistor.

The MOS System under External Bias23-Feb-16BVM ET28As a practical definition, the surface is said to be inverted when the density of mobile electrons on the surface becomes equal to the density of holes in the bulk (p-type) substrate.This condition requires that the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi potential. Further increase in the potential will increase in the mobile electrons but not the width of the depletion region.So , at the surface inversion, we can able to see the maximum depletion region depth.

The MOS System under External Bias23-Feb-16BVM ET29So at surface inversion, the maximum depletion region depth can be given by,

The creation of conducting surface inversion layer through externally applied gate bias is an essential phenomenon for current conduction in MOS transistors.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET30The basic structure of an n-channel MOSFET is shown in Fig.3.8.The surface of the substrate region between the drain and the source is covered with a thin oxide layer, and the metal(or polysilicon) gate is deposited on the top of this gate dielectric.The midsection of the device can easily be recognized as the basic MOS structure which was examined in the previous sections.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET31

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET32A conducting channel will eventually be formed through applied gate voltage in the section of the device between the drain and the source diffusion regions.The distance between the drain and source diffusion region is the channel length L, and the lateral extent of the channel(perpendicular to the length dimension) is the channel width W. The thickness of oxide layer covering the channel region, tox, is also an important parameter.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET33A MOS transistor which has no conducting channel region at zero gate bias is called an enhancement type MOSFET.If a conducting channel already exists at zero gate bias, on the other hand, the device is called a depletion type MOSFET.P-type substrate is called n-channel MOSFETN-type substrate is called p-channel MOSFET.We can able to see all the terminals of the n-channel MOSFET and p- channel MOSFET in the diagram 3.9 as a symbolic representation.


Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET35Now we check the electrical behavior of n-channel MOSFET by applying the various voltages.As shown in fig 3.10. The source, the drain, and the substrate terminals are all connected to ground.A positive gate to source voltage is then applied to the gate in order to create the conducting channel underneath the gate.With this bias arrangement, the channel region between the source and the drain diffusions behaves exactly the same as for the simple MOS structure we examined.


Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET37For small gate voltage levels, the majority carriers(holes) are repelled back into the substrate, and the surface of the p-type substrate is depleted.Since the surface is devoid of any mobile carriers, current conduction between the source and the drain is not possible.Now assume that the gate-to-source voltage is further increased. As soon as the surface potential in the channel reaches negative fermi potential value(inverse layer), surface inversion will be established, and a conducting n-type layer will form between the source and the diffusion regions as shown in fig. 3.11.



Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET40This channel now provides an electrical connection between the two n+ regions, and it allows current flow.(fig.3.12)The value of the gate to source voltage needed to cause surface inversion (to create the conducting channel) is called the threshold voltage. Any gate to source voltage smaller than threshold voltage is not sufficient to establish an inversion layer.Increasing the gate to source voltage above and beyond the threshold voltage will not affect the surface potential and the depletion region depth.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET41The Threshold VoltageBasically four parameters are affecting the threshold voltage in MOS structure1. work function difference between the gate and the channel and it is given by

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET42The work function difference between the gate and the channel reflects the built in potential of the MOS system, which consist of the p-type substrate, the thin silicon dioxide layer, and the gate electrode.2. The gate voltage component to change the surface potential.The external applied voltage must be changed to achieve surface inversion, i.e., to change the surface potential by

This will be the second component of the threshold voltage.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET433. The gate voltage component to offset the depletion region chargeWhich is due to the fixed acceptor ions located in the depletion region near the surface.We can calculate the depletion region charge density at surface inversion using (3.12)

If the substrate (body) is biased at a different voltage level than the source, which is at ground potential (reference),

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET44Then the depletion region charge density can be expressed as a function of the source to substrate voltage ,

The component that offsets the depletion region charge is then equal to ,

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET45The Gate oxide capacitance per unit area is given by ,

4. The voltage component to offset the fixed charges in the gate oxide and in the silicon oxide interface. There always exists a fixed positive charge density at the interface between the gate oxide and the silicon substrate, due to impurities and/or lattice imperfections at the interface.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET46The gate voltage component that is necessary to offset this positive charge at the interface is ,

So, finally combining all the four components which are affecting the threshold voltage can be written as(for zero substrate bias),

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET47For nonzero substrate bias,

The generalized form of the threshold voltage can also be written as,

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET48Note that in this case, the threshold voltage differs only by an additive term.This substrate bias term is a simple function of the material constants and of the source to substrate voltage.

Thus, the most general expression of the threshold voltage can be found as follows:


Where, the parameter ,

Is the substrate bias (or body effect) coefficient.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET50Some of the terms have different polarities for nMOS and for pMOS. SpecificallyFermi potential level, depletion charge densities, substrate bias coefficient and substrate bias voltage.Note that the exact value of the threshold voltage of an actual MOS transistor can not be determined using the equation 3.23 in most practical cases, due to primarily to uncertainties and variation of the doping concentrations, the oxide thickness, and the fixed oxide interface charge.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET51Note that, using selective ion implantation into the channel, the threshold voltage of an n-channel MOSFET can also be made negative. This means that the resulting nMOS transistor will have a conducting channel at gate to source voltage equals to zero, enabling current flow between its source and drain terminals as long as Vgs is larger than the negative threshold voltage. Such device is called depletion type(or normally ON) n-channel MOSFET.Figure 3.13 shows a symbolic diagram of n channel depletion type MOSFET.


Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET53Example.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET54MOSFET Operation: A Qualitative ViewThe basic structure of the n-channel MOS (nMOS) transistor built on a p-type substrate was shown in figure 3.8. (accumulation) (depletion)(no current flow) (inversion)Now we will examine the electrical behavior of nMOS by changing the value of Vds.

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET55If small positive drain voltage is applied, a drain current will flow from source to drain through the conducting channel.This operation mode is called the linear mode, or the linear region.Thus, in linear region operation, the channel region act as a voltage controlled resistor.As the drain voltage is increases, the inversion layer charge and the channel and the channel depth at the drain end start to decrease. (figure.3.14)


Fig.3.14: cross sectional view of an n-channel MOS transistor

Structure and Operation of MOS Transistor (MOSFET)23-Feb-16BVM ET57Eventually, for drain to source voltage will be equal to drain to source saturation voltage, the inversion charge at the drain is reduced to zero, which is called the pinch off point. Fig 3.14 bBeyond the pinch off point, i.e for drain to source voltage is greater than the drain to source voltage saturation, the depletion region grows toward the source with increasing drain voltages.This operation mode of the MOSFET is called the saturation mode or saturation region.Because of this the effective channel length is reduced as the inversion layer near to the drain vanishes. From this fundamentals we can able to get the I-V characteristics of the MOSFET.





MOSFET Current Voltage Characteristics.23-Feb-16BVM ET60The analytical derivation of the MOSFET current-voltage relationship for various bias conditions requires that several approximations be made to simplify the problem,Here we will use the Gradual channel approximation (GCA) for establishing the MOSFET current voltage relationships, which will effectively reduce the analysis to one dimensional current flow problem.GCA have also its limitations, especially for small geometry of MOSFETs. We will examine some of them and its remedies.

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET61GCATo begin with the current flow analysis, consider the cross sectional view of the n-channel MOSFET operating in the linear mode as shown in fig. 3.15

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET62

Also, its is assumed that the entire channel region between the source and the drain is inverted,.

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET63The channel current ( drain current) is due to electrons in channel region traveling from the source to the drain under the influence of the lateral electric field component Ey. Let Qi(y) be the total mobile electron charge in the surface inversion layer. This charge can be expressed as a function of the gate to source voltage and of the channel voltage as follows.,

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET64Figure.3.16 shows the spatial geometry of the surface inversion layer and indicates its significant dimensions.Now consider the incremental resistance dR of the differential channel segment shown in fig 3.16.Assuming that all mobile electrons in the inversion layer have constant surface mobility , the incremental resistance can be expressed as follows.


MOSFET Current Voltage Characteristics.23-Feb-16BVM ET66The electron surface mobility used in eq 3.28 depends on the doping concentration of the channel region, and its magnitude is typically about one-half of the of the bulk electron mobility.We will assume that the channel current density is uniform across this segment. According to the ohm's law.

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET67The equation 3.29 can now be integrated along the channel., i.e., from y=0 to y=L, using the boundary condition given (3.25).

After simplification of eqn 3.30., we get

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET68Assuming that Vc is the only variable in eqn 3.31., we get,

Above equation represent the drain current as a simple second order function of the two external voltages and this equation can also be rewritten as.,

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET69OR,

Where,

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET70The drain current equation given in (3.33) is the simplest analytical voltage current relationship. The drain current is not valid beyond the linear region/saturation region boundary,. For

This saturation drain current level can be found simply by substituting (3.37) into 3.32We get,


Thus, the drain current becomes a function of the gate to source voltage beyond the saturation boundary.Figure 3.17 shows the typical current versus drain voltage characteristics of an n-channel MOSFET, as described by the current equations 3.32 and 3.38.



MOSFET Current Voltage Characteristics.23-Feb-16BVM ET74Channel length ModulationThe inversion layer charge at the source end of the channel is,

And the inversion layer charge at the drain end of the channel is ,

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET75Now at the edge of saturation we get,

The inversion layer charge at the drain end becomes zero, according to (3.40). Its not actually become zero but becomes very small.

Thus, we can state that under the bias condition given in3.41, the channel is pinched off at the drain end.

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET76Now if we increase the drain to source voltage more than saturation voltage, we can able to see the effect on channel length, see the diagram no, 3.19

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET77The effect on channel length is,(channel length modulation)

And the channel voltage at this edge will be ,

The channel current can be found using 3.38

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET78We can modify the 3.45 by using the equation 3.43, we get,

Where,

MOSFET Current Voltage Characteristics.23-Feb-16BVM ET79For simplification,

Here lemda is an empirical parameter and its also known as channel length modulation coefficient. Now assuming that 1 leads to the reduction of the area occupied by the transistor by a factor of S^2.Here to understand the effects of scaling upon the operational characteristics, we will examine two different scaling options in the following sections.

MOSFET scaling and small-geometry effects23-Feb-16BVM ET83

MOSFET scaling and small-geometry effects23-Feb-16BVM ET84Full Scaling ( Constant-Field Scaling)This scaling option attempts to preserve the magnitude of internal electric fields in the MOSFET, while the dimension are scaled down by a factor of S. The Poisson equation describing the relationship between charge densities and electric fields dictates that the charge densities must be increased by a factor of S in order to maintain the field conditions. Table 3.2 shows the comparison of old and new dimensions.


MOSFET scaling and small-geometry effects23-Feb-16BVM ET86The gate oxide capacitance per unit area is changed as follows

The aspect ration W/L of the MOSFET will remain unchanged under scaling. The linear mode drain current of the scaled MOSFET can now be found as:

MOSFET scaling and small-geometry effects23-Feb-16BVM ET87Similarly, the saturation-mode drain current is also reduced by the same scaling factor.

The instantaneous power dissipated by the device before scaling can be found as:

MOSFET scaling and small-geometry effects23-Feb-16BVM ET88Notice that full scaling reduces both the drain current and the drain to source voltage by factor of S; the power dissipation of the transistor will be reduced by the factor S^2.

This significant reeducation of the power dissipation is one of the most attractive features of full scaling.This scaling also affect the capacitance of the MOSFET .


MOSFET scaling and small-geometry effects23-Feb-16BVM ET90Constant Voltage scalingIn constant voltage scaling, all dimensions of the MOSFET are reduced by a factor of S, as in full scaling.The power supply voltage and the terminal voltages remain unchanged.Under this scaling the device characteristics are significantly different compare to those in full scaling.The linear mode drain current can be written as,

MOSFET scaling and small-geometry effects23-Feb-16BVM ET91The drain current ,

Also, the saturation mode drain current will be increased by a factor of S after constant voltage scaling,

MOSFET scaling and small-geometry effects23-Feb-16BVM ET92Since the drain current is increased by a factor of S while the drain to source voltage remains unchanged, the power dissipation of the MOSFET increases by a factor of S.

MOSFET scaling and small-geometry effects23-Feb-16BVM ET93We can see the effect after scaling on other parameters also,

Constant voltage scaling may be preferred over full scaling in many practical cases because of the external voltage level constraints.

MOSFET scaling and small-geometry effects23-Feb-16BVM ET94But in constant voltage scaling, large increase in current and power density may eventually causes serious reliability problems for the scaled transistor, such as electro migration, hot carrier degradation, oxide breakdown, and electrical over stress.Due to this scaling, the current equations have to be modified accordingly. In the following, we will briefly investigate some of these small geometry effects.

MOSFET scaling and small-geometry effects23-Feb-16BVM ET95Short Channel Effects:As a working definition, a MOS transistor is called a short channel device if its channel length is on the same order of magnitude as the depletion region thicknesses of the source and drain junction. The short channel effects that arise in this case are attributed to two physical phenomena, (i) the limitations imposed on electron drift characteristics in the channel,(ii) the modification of the threshold voltage due to the shortening channel length.

MOSFET scaling and small-geometry effects23-Feb-16BVM ET96Not that the lateral electric field Ey along the channel increases, as the effective channel length is decreased. The effective channel length Leff will be reduced due to channel length shortening.

Since the channel end voltage is equal to saturation drain voltage , the saturation current can be found a follows;

MOSFET Capacitances23-Feb-16BVM ET97In order to examine the transient (AC) response of MOSFETs and digital circuits consisting of MOSFETs, we have to determine the nature and the amount of parasitic capacitances associates with the MOS transistor.Most of the capacitances in MOS are not Lumped but are distributed,Here in figure 3.29 shows the top view and cross sectional view of the n channel MOSFET.

MOSFET Capacitances23-Feb-16BVM ET98

MOSFET Capacitances23-Feb-16BVM ET99We are studying the parasitic device capacitances, we will have to become more familiar with the top view of the MOSFET.From the diagram we can able to get the actual length(channel length can be calculated)

The typical diffusion region length is denoted by Y as shown in figure 3.29.

MOSFET Capacitances23-Feb-16BVM ET100The p+ (channel stop region) is to prevent the formation of any unwanted (parasitic) channels between the neighboring n+ diffusion regions.We will identify the parasitic capacitances associated with this typical MOSFET structure as lumped equivalent capacitances observed between the device terminals. (figure.3.30)Basically these capacitances are classified in two groups, (1) oxide related capacitances and (2) Junction capacitances.


MOSFET Capacitances23-Feb-16BVM ET102The two overlap capacitances that arise as a result of this structural arrangement are,

Where W is source and drain diffusion region width.These both the capacitances are not depending on the bias conditions, they are voltage independent,

MOSFET Capacitances23-Feb-16BVM ET103Now, If we consider the three mode of the MOSFETs, starting with the cut off mode, the surface is not inverted.Consequently, there is not conducting channel that links the surface to source and to the drain. So we get Cgs=Cgd=0.And the gate to substrate capacitance can be approximated by

For more understanding, see the diagram number 3.31(a)


MOSFET Capacitances23-Feb-16BVM ET105Now, in a linear mode, the inverted channel extends across the MOSFET, This conducting inversion layer on the surface effectively shields the substrate from the gate electric field; thus Cgb=0. In this case we can able to get,

This can be seen in the figure 3.31(b)


MOSFET Capacitances23-Feb-16BVM ET107Now , when operating in the saturation mode, since the source is still linked to the conducting channel, we get Cgb=0, and finally we get the approximated value is

The diagram shows the effect on capacitance while in saturation mode(figure 3.31_C)


MOSFET Capacitances23-Feb-16BVM ET109The table 3.6 shows the summery of the approximate oxide capacitance values in three different operating modes of the MOSFET.

MOSFET Capacitances23-Feb-16BVM ET110The variation of the distributed parasitic oxide capacitances as functions of the gate to source voltage is also shown in fig. 3.32

MOSFET Capacitances23-Feb-16BVM ET111We have to combine the distributed Cgs and Cgd.The sum of all voltage dependent gate oxide capacitances ( Cgb+Cgs+Cgd) has a minimum value in saturation mode and maximum value in cut off and linear mode. For simple calculations, where all three capacitances can be considered to be connected in parallel, we can use the below value as a sum of all the gate oxide capacitances of MOSFET.

MOSFET Capacitances23-Feb-16BVM ET112Junction capacitancesNow, we consider the voltage dependent source substrate and drain substrate junction capacitances, Csb and Cdb respectively. The calculation of the associated junction capacitances is complicated by the three dimensional shape of the diffusion region that form the source substrate and the drain substrate junction as shown in figure 3.33.


MOSFET Capacitances23-Feb-16BVM ET114Table 3.7 shows the all 5 junction capacitance area and type,

MOSFET Capacitances23-Feb-16BVM ET115To calculate depletion capacitance of a reverse biased abrupt pn junction, consider first the depletion region thickness Xd, and reverse bias voltage V, we get, Xd is

Where the built in junction potential is calculated as,

MOSFET Capacitances23-Feb-16BVM ET116Note that the junction is forward biased for a positive bias voltage V, and reverse bias for the negative voltage V. The depletion region charge stored can be written as ,

Here, A indicates the junction area. The junction capacitance associated with the depletion region is defined as

MOSFET Capacitances23-Feb-16BVM ET117By differentiating equation 3.101with respect to bias voltage V, we can now obtain the junction capacitance,

This equation can be rewritten in a more general form,

MOSFET Capacitances23-Feb-16BVM ET118The parameter m in eq 3.104 is called the grading coefficient. Its value is equal to for an abrupt junction, and 1/3 for a linear graded junction profile. The zero bias junction capacitance per unit area is defined by

The problem of estimating capacitance values under changing bias conditions can be simplified, if we calculate a large signal average junction capacitance instead.

MOSFET Capacitances23-Feb-16BVM ET119The equivalent large signal capacitance can be defined as follows:

By substituting 3.104 to 3.106, we get

MOSFET Capacitances23-Feb-16BVM ET120For a special case of abrupt pn-junctions the equation becomes

This equation can be rewritten in as simpler form by finding a dimensionless coefficient as follows,

Outcomes23-Feb-16BVM ET121From this unit, the understanding of the Electrical behavior of MOSFET become clear. The more focus on the variations of the voltages and its effects on current and power as well as the changes in the capacitances of the MOSFETs are also become more clear. The electrical behavior can be understood in three of the MOSFET modes named cut-off, linear and saturation.

References23-Feb-16BVM ET122Book: CMOS Digital Integrated Circuit Design - Analysis and Design by S.M. Kang and Y. Leblebici.