VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT

OF

ELECTRONICS AND INSTRUMENTATION ENGINEERING

QUESTION BANK

VII SEMESTER

EC6601-VLSI DESIGN

Regulation – 2013

Academic Year 2017– 2018

Prepared by

Mr.K.R.Ganesh, Assistant Professor (O.G ) / EIE

Ms. R. Umamaheswari, Assistant Professor (O.G) / EIE

UNIT I - MOS TRANSISTOR PRINCIPLE

NMOS and PMOS transistors, Process parameters for MOS and CMOS, Electrical properties of

CMOS circuits and device modeling, Scaling principles and fundamental limits, CMOS inverter

scaling, propagation delays, Stick diagram, Layout diagrams

PART – A

S.No Questions BT

Level Competence

1 Write the significance of lambda based design rules. BTL- 1 Remember

2 Define body bias effect. BTL- 1 Remember

3 What is threshold voltage? BTL- 1 Remember

4 What is Latch-up? How to prevent latch up? BTL- 1 Remember

5 State channel length modulation. Write down the equation for

describing the channel length modulation effect in NMOS

transistors.

BTL- 1 Remember

6 State the 3 modes involved in the operation of an

enhancement transistor.

BTL- 1 Remember

7 Express about propagation delay of a CMOS inverter. BTL- 2 Understand

8 Differentiate enhancement and depletion mode devices. BTL- 2 Understand

9 Give the types of scaling in CMOS technology. BTL- 2 Understand

10 Compare the effect of scaling on MOSFET device

parameters.

BTL- 2 Understand

11 Define noise margin. Illustrate how it can be obtained from

the transfer characteristics of a CMOS Inverter.

BTL- 3 Apply

12 Draw the equivalent circuit structure of LEVEL1 MOSFET

model in SPICE.

BTL- 3 Apply

13 Draw the DC transfer characteristics of CMOS inverter. BTL- 3 Apply

14 Point out the types of oxidation. BTL- 4 Analyze

15 Mention the advantages of EBL pattern generation. BTL- 4 Analyze

16 Mention the non-ideal IV effects of MOS transistor. BTL- 4 Analyze

17 Predict the factors influencing the drain current. BTL- 5 Evaluate

18 Compare CMOS and Bipolar technologies. BTL- 5 Evaluate

19 Develop a stick diagram for NAND gate. BTL- 6 Create

20 If the nominal threshold voltage of NMOS transistor in an

180nm process is 0.4V and doping level is 8x1017

cm-3

. What

is the body voltage?

BTL- 6 Create

PART B

1 (i) Describe the equation for source to drain current in the three

regions of operation of a MOS transistor and draw the VI

characteristics. (8)

(ii) Describe in detail about body effect and its effect in MOS

device. (8)

BTL-1 Remember

2 (i) Examine about the Non ideal I-V characteristics of MOS

transistor. (8)

(ii) Describe the important properties used for the estimation of

resistance in MOS resistance model. (8)

BTL-1 Remember

3 Describe the following concepts:

(i) Device model and device characterization (8)

(ii) SPICE based circuit simulation (8)

BTL-1 Remember

4 Describe about the need of scaling, scaling principles and

fundamental limits on CMOS inverter scaling. (16) BTL-1 Remember

5 Discuss about the lambda based design rules for NMOS and

CMOS transistors. (16) BTL-2 Understand

6 Discuss about the following MOS capacitance model: (4X4)

(i) Simple MOS capacitance model.

(ii) Detailed MOS gate capacitance model.

(iii) MOS device capacitance.

(iv) Detailed MOS diffusion capacitance model.

BTL-2 Understand

7 (i) Discuss the principles of constant field and lateral scaling.

Write the effects of the above scaling methods on the device

characteristics. (8)

(ii) Explain the DC transfer characteristics of a CMOS inverter

with necessary conditions for the different regions of operation.

(8)

BTL-2 Understand

8 (i) Explain the characteristics of CMOS inverter with its

transfer characteristics. (8)

(ii) Construct the layout for 2 input NAND and AND gates

using CMOS inverters. (8)

BTL-3

Apply

9 Draw the circuit layout and stick diagram for

(i) Two input XOR gate (8)

(ii) CMOS inverter (8)

BTL-3 Apply

10

Explain the operation of following MOS transistor:

(i) NMOS enhancement (8)

(ii) PMOS enhancement (8)

BTL-4 Analyze

11 (i) Explain the different steps involved in n-well CMOS

fabrication process with neat diagrams. (8)

(ii) Derive the noise margins for a CMOS inverter. (8)

BTL-4 Analyze

12 Explain in detail about second order effects of MOS transistor.

(16) BTL-4 Analyze

13 (i) Consider an NMOS having electron mobility of µn

=540cm2/V–Sec. Calculate the process

transconductance for the gate oxide thickness of 12 nm

and 8 nm. (8)

(ii) An nMOS transistor has the following parameters: gate

oxide thickness= 10nm, relative permittivity of gate

oxide=3.9, electron mobility= 520 cm2/V-sec, threshold

voltage= 0.7 V, permittivity of free space= 8.85 x 10-14

F/cm and (W/L)=8. Calculate the drain current when

(VGS = 2V and VDS =1.2 V) and also compute the gate

oxide capacitance per unit area. Note that W and L refer

to the width and length of the channel respectively.

(8)

BTL-5 Evaluate

14 Realize the function Y = (A + B + C)D using CMOS

compound gate. Draw the stick diagram and layout diagram.

(16)

BTL-6 Create

UNIT II - COMBINATIONAL LOGIC CIRCUITS

Examples of Combinational Logic Design, Elmore’s constant, Pass transistor Logic,

Transmission gates, static and dynamic CMOS design, Power dissipation – Low power design

principles

PART - A

S.No Questions BT

Level Competence

1 What is a transmission gate? BTL- 1 Remember

2 List the advantages of pass transistor. BTL- 1 Remember

3 Define Transistor sizing problem. BTL- 1 Remember

4 What are the advantages of using pseudo-nMOS gate instead

of full CMOS gate?

BTL- 1 Remember

5 State the types of power dissipation. BTL- 1 Remember

6 What are critical paths? BTL- 1 Remember

7 Give Elmore delay expression for propagation delay of an

inverter.

BTL- 2 Understand

8 Why is the transmission of logic 1 degraded as it passes

through a NMOS pass transistor?

BTL- 2 Understand

9 Write the expressions for the logical effort and parasitic delay

of n- input NOR gate.

BTL- 2 Understand

10 Estimate how dynamic power can be reduced. BTL- 2 Understand

11 Mention the two phases of operation in a dynamic CMOS

logic.

BTL- 3 Apply

12 Draw the symbol of transmission gate. Mention the

disadvantages of CMOS transmission gate.

BTL- 3 Apply

13 Mention the drawbacks of dynamic logic. BTL- 3 Apply

14 Prioritize the criteria needed for low power logic design. BTL- 4 Analyze

15 Point out the factors that produce dynamic power dissipation. BTL- 4 Analyze

16 Analyze about the factors that cause static power dissipation

in CMOS circuits.

BTL- 4 Analyze

17 Why single phase dynamic logic structure cannot be

cascaded? Justify.

BTL- 5 Evaluate

18 Realize OR and NOR logic function using differential cascade

voltage switch logic.

BTL- 5 Evaluate

19 Implement a 2:1 Multiplexer using pass transistor. BTL- 6 Create

20 Develop a 2-input XOR gate using transmission gates. BTL- 6 Create

PART-B

1 What are the sources of power dissipation in CMOS and

discuss various design techniques to reduce power dissipation

in CMOS? (16)

BTL-1 Remember

2 (i) Describe the properties and operation of dynamic CMOS

logic with neat diagram. (8)

(ii) List the various application of dynamic CMOS logic. (8)

BTL-1 Remember

3 (i)Explain the static and dynamic power dissipation in CMOS

circuits with necessary diagrams and expressions. (8)

(ii) Derive an nMOS inverter pair delay whose transistor size is

4:1. (8)

BTL-1 Remember

4 Describe the following concepts: (4x4)

(i) RC delay models.

(ii) Elmore delay model.

(iii) Linear delay model.

(iv) Logical effort delay model.

BTL-1 Remember

5 (i) Compare static and dynamic CMOS logic circuit with

example. (8)

(ii) Discuss about pseudo-nMOS gates with neat circuit

diagram. (8)

BTL-2 Understand

6 (i) Discuss about the principles of Low power logic design in

CMOS circuits. (8)

(ii) Realize the operation of ratioed circuits with neat diagram.

(8)

BTL-2

Understand

7 (i) Discuss in detail about the characteristics of CMOS

transmission gate. (8)

(ii) Express about delay estimation, logical effort and transistor

sizing with example. (8)

BTL-2

Understand

8 Draw and explain about realization of inverters and basic gates

using pass transistor logic. (16)

BTL-3 Apply

9 With neat sketch, illustrate the operation of pass transistor DC

characteristics. (16)

.BTL-3 Apply

10 (i) Describe the basic principle of operation of dynamic CMOS,

domino and NP domino logic with neat diagrams. (8)

(ii) Explain about DCVSL logic with suitable example. (8)

BTL-4 Analyze

11 (i) Explain the operation, important properties, advantages and

limitations of static CMOS design. (8)

(ii) Explain about the problem of charge sharing and the

methods to overcome it. (8)

BTL-4 Analyze

12 (i) Explain the domino and dual rail domino logic families with

neat diagrams. (8)

(ii) Explain the multiple output and zipper domino logic. (8)

BTL-4 Analyze

13 (i) Realize the following function using CMOS: (8)

(a) F (A, B, C) = A’BC + AB’C + ABC’

(b) Y= (A+B) (C+D)

(ii) Draw the static CMOS logic circuit for the following

expression: (8)

(a)

(b)

BTL- 5 Evaluate

14 (i) Design a D-latch using transmission gate. (8)

(ii)Design a 1-bit dynamic inverting and non-inverting register

using pass transistor. (8)

BTL- 6 Create

UNIT III- SEQUENTIAL LOGIC CIRCUITS

Static and Dynamic Latches and Registers, Timing issues, pipelines, clock strategies, Memory

architecture and memory control circuits, Low power memory circuits, Synchronous and

Asynchronous design

PART - A

S.No Questions BT

Level Competence

1 What are the timing parameters for electronic memories? BTL-1 Remember

2 List the timing metrics for sequential circuits. BTL-1 Remember

3 Tabulate the classification of semiconductor memory. BTL-1 Remember

4 Define clock jitter. BTL-1 Remember

5 What is clocked CMOS register? BTL-1 Remember

6 What are synchronizers? Enumerate its features. BTL-1 Remember

7 Differentiate combinational and sequential logic circuits. BTL-2 Understand

8 Is D-flip-flop applicable for counter applications? Why? BTL-2 Understand

9 Express time borrowing concepts in transparent latches. BTL-2 Understand

10 Estimate clock skew in synchronous design. BTL-2 Understand

11 Draw the Voltage Transfer Characteristics of two cascaded

inverters.

BTL 3 Apply

12 Mention the advantages of using a block address in memory

design.

BTL-3 Apply

13 Draw the block diagram of a Finite State Machine. BTL-3 Apply

14 Classify digital systems based on timing characteristics. BTL-4 Analyze

15 Point out the advantages of two phase clocking scheme. BTL-4 Analyze

16 Point out the concepts of pipelining. BTL-4 Analyze

17 Obtain the functional composition of a PLL. BTL-5 Evaluate

18 Compare and contrast synchronous design and asynchronous

design.

BTL-5 Evaluate

19 Develop a switch level schematic of multiplexer based NMOS

latch using NMOS only pass transistors.

BTL-6 Create

20 Design a one-transistor DRAM cell. BTL-6 Create

PART B

1 (i)Describe the architecture of an N-word memory. (8)

(ii) Describe the operation of various memory peripheral

circuitries. (8) BTL-1 Remember

2 (i) Describe the Bi-stability principle associated with static

latches and registers. (8)

(ii) Examine the differences between Static and Dynamic

Memory. (8)

BTL-1

Remember

3 (i) What are the different approaches to reduce power

dissipation in memories? (8)

(ii) What are the challenges involved in an asynchronous

design? Can these challenges be overcome using a self-timed

logic? (8)

BTL-1 Remember

4 (i) What is the drawback of transmission gate register? Explain

the various approaches to overcome it. (8)

(ii) Describe the operation of a Dynamic Transmission Gate

Edge Triggered Register. (8)

BTL-1 Remember

5 (i) Illustrate the impact of clock skew and jitter on the

performance of a sequential system (8)

(ii) Discuss about the basic concept of clock synthesis and

synchronization using Phase –Locked loop. (8)

BTL-2 Understand

6 (i) Distinguish various clocking strategies used in chip design.

(8)

(ii) How can one design a register that is insensitive to clock-

skew? (8)

BTL-2 Understand

7 (i) Summarize about the concept and implementation of

Synchronizer and arbiters. (8)

(ii) How can we build latches using multiplexers? Discuss their

operation in detail. (8)

BTL-2 Understand

8 (i) Mention about the common approaches for constructing an

edge triggered register. (8)

(ii) Explain the operation of master-slave based edge triggered

register. (8)

BTL-3 Apply

9 (i) Draw and explain the operation of conventional, pulsed and

resettable latches. (8)

(ii)Explain th operation of True single phase clocked register

with a neat diagram. (8)

BTL-3 Apply

10 Explain in detail about various static latches and registers.

(16) BTL-4 Analyze

11 Explain in detail various pipelining approaches to optimize

sequential circuits. (16) BTL-4 Analyze

12 (i) What kinds of failures are caused by clock overlap? (4)

(ii) Explain the various approaches adopted to overcome clock

overlap with neat schematics. (12)

BTL-4 Analyze

13 Explain the concepts of timing issues and pipelining.

(16) BTL-5 Evaluate

14 Explain the operation of Static SR flip flops built using NOR

and NAND gates. Also, derive the truth table for such an

implementation. (16)

BTL-6 Create

UNIT IV- DESIGNING ARITHMETIC BUILDING BLOCKS

Data path circuits, Architectures for ripple carry adders, carry look ahead adders, High speed

adders, accumulators, Multipliers, dividers, Barrel shifters, and speed and area trade off

PART - A

S.No Questions BT

Level Competence

1 What is meant by bit-sliced data path organization? BTL-1 Remember

2 List out the components of data path. BTL-1 Remember

3 What is the arithmetic structures derived from a full adder? BTL-1 Remember

4 Define Vector merging adder. BTL-1 Remember

5 Mention the principle of any one fast multiplier. BTL-1 Remember

6 List the uses of Clock gating. BTL-1 Remember

7 Give a neat sketch on Manchester carry gates. BTL-2 Understand

8 Express the inverting property of full adder. BTL-2 Understand

9 Determine the regularity of 4 X 4 barrel shifter. BTL-2 Understand

10 Give the applications of high speed adder. BTL-2 Understand

11 Draw the schematic for sleep transistors used on both supply

and ground. BTL-3 Apply

12 Mention the draw backs of a static adder circuit. BTL-3 Apply

13 Calculate the propagation delay of n-bit carry select adder. BTL-3 Apply

14 Compare constant throughput and variable throughput in

active & leakage mode.

BTL-4

Analyze

15 Compare dadda multiplier and booth multiplier. BTL-4 Analyze

16 Select the method which is adopted to reduce power in sleep

mode. BTL-4 Analyze

17 Express Ripple carry adder using dot operator. BTL-5 Evaluate

18 Check whether barrel shifter is very useful in the designing of

arithmetic blocks. BTL-5 Evaluate

19 Create a partial product selection table using modified booth’s

recoding. BTL-6

Create

20 Generalize the Concept of logarithmic look ahead adder. BTL-6 Create

PART-B

1 (i) Describe ripple carry adder and derive the worst case delay

with example. (8)

(ii) Describe the inversion property of full adder. (8)

BTL-1 Remember

2 Explain the operation of a basic 4-bit adder; also Describe the

different approaches of improving the speed of adder.

(16)

BTL-1 Remember

3 Describe the implementation of a Manchester Carry chain

adder. (16) BTL-1 Remember

4 List the logic design considerations of binary adder and

explain the following types:

(i) Carry skip adder (8)

(ii) Carry save adder (8)

BTL-1 Remember

5 (i) Explain the concept of carry look ahead adder with neat

diagram. (8)

(ii) Discuss the details about speed and area trade off. (8)

BTL-2 Understand

6

(i) Describe the concept of monolithic and logarithmic look

ahead adder. (8)

(ii) Discuss the data paths in digital processor architectures.

(8)

BTL-2 Understand

7 (i) Discuss how power can be reduced in the standby mode in

the design of arithmetic unit. (8)

(ii) Describe in detail about various Run-time power

management schemes. (8)

BTL-2 Understand

8 (i) Demonstrate how to reduce the number of generated partial

products by half. (8)

(ii) Explain the methods to accumulate partial products in

array form. (8)

BTL-3 Apply

9 (i) What are the methods adopted to perform division in a

digital IC? Make a comparison between them. (8)

(ii) Describe the design approach adopted in a logarithmic

shifter. (8)

BTL-3 Apply

10 Classify circuit design considerations of full adder and

explain the following:

(i) Mirror adder (8)

(ii) Transmission gate adder (8)

BTL-4 Analyze

11 Explain the concept of modified Booth multiplier with a

suitable example. (16) BTL-4 Analyze

12 Design a 16 bit carry bypass and carry select adder and

discuss their features. (16) BTL-4 Analyze

13 Explain the operation of Booth multiplication with suitable

examples, And Justify how Booth algorithm speeds up the

multiplication process. (16)

BTL-5 Evaluate

14 Design a 4 X 4 array multiplier and write down the equation

for delay. (16) BTL-6 Create

UNIT V- IMPLEMENTATION STRATEGIES

Full custom and Semi-custom design, Standard cell design and cell libraries, FPGA building

block architectures, FPGA interconnect routing procedures.

PART - A

S.N

o Questions

BT

Level Competence

1 What is the standard cell based ASIC design? BTL-1 Remember

2 What is meant by CBIC? BTL-1 Remember

3 Name the elements in configuration logic block. BTL-1 Remember

4 What is an anti-fuse? State its merits and demerits. BTL-1 Remember

5 List out three main parts of FPGA & what is PMS? BTL-1 Remember

6 Define OEM. BTL-1 Remember

7 Distinguish between PAL and PLA. BTL-2 Understand

8 State the features of full custom design. BTL-2 Understand

9 What are feed through cells? State its uses. BTL-2 Understand

10 Give a note on tape out of chip. BTL-2 Understand

11 Mention the objectives and goals of System Partitioning. BTL-3 Apply

12 Illustrate the advantages and disadvantages of FPGA compared

to ASIC. BTL-3 Apply

13 Show the advantages and disadvantages of cell based design

methodology. BTL-3 Apply

14 Differentiate between Altera MAX 9000 and Altera FLEX

interconnects architecture. BTL-4 Analyze

15 Compare FPGA and CPLD. BTL-4 Analyze

16 Compare between fine-grain and coarse-grain architecture of

FPGA. BTL-4 Analyze

17 Obtain the different types of interconnections present in Xilinx

FPGA. BTL-5

Evaluate

18 Evaluate speed grading. BTL-5 Evaluate

19 Integrate the concept of segmented Channel routing. BTL-6 Create

20 Design a primitive gate array cell. BTL-6 Create

PART B

1 Describe the following types of ASIC:

(i) Full custom ASIC (8)

(ii) Semi-custom ASIC (8)

BTL-1 Remember

2 Describe briefly about Gate-Array based ASIC’s design with

neat diagrams. (16) BTL-1 Remember

3 (i) Explain the Configurable Logic Block and IO block of

Xilinx XC4000 FPGA. (8)

(ii) List the features of Xilinx XC4000 FPGA. (8)

BTL-1 Remember

4 (i) Explain about building block architecture of FPGA. (8)

(ii) Write short notes on routing procedures involved in FPGA

interconnect. (8)

BTL-1 Remember

5 Discuss the different types of programming technology used in

FPGA design. (16) BTL-2 Understand

6 With neat sketch explain the CLB, IOB and programmable

interconnects of an FPGA device. (16) BTL-2 Understand

7 Briefly explain the semi-custom ASIC with its classification.

(16) BTL-2 Understand

8 (i) Illustrate the concepts of Mask programmable arrays. (8)

(ii) Identify the components involved in constructing a voltage

output macro cell. (8)

BTL-3 Apply

9 Define and explain briefly about different approaches of

programmable wiring with neat diagrams. (16) BTL-3 Apply

10 Explain about different types of ASIC with neat diagram.

(16) BTL-4 Analyze

11 With design flow, explain the sequence of steps involved in the

ASIC design process. (16) BTL-4 Analyze

12 Explain the interconnect architectures of the following:

(i) Altera Max series (8)

(ii) Xilinx XC40XX series (8)

BTL-4 Analyze

13 (i) Compare and contrast about EPROM and EEPROM

technology. (8)

(ii) Summarize about programming of Programmable Array

Logic. (PAL) (8)

BTL-5 Evaluate

14 (i) Design an LUT-Based Logic Cell. (8)

(ii) Discuss the Classification of prewired arrays. (8) BTL-6 Create

***************