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• Sam Palermo Analog & Mixed-Signal Center

Texas A&M University

ECEN474: (Analog) VLSI Circuit Design Fall 2010

Lecture 5: MOS Transistor Modeling

• Announcements

• Lab 1 this week

• Reading for next time • Johns/Martin 2.1, 2.3-2.5

2

• Agenda

• Threshold voltage dependencies on W,L • Temperature dependencies • Process corners • Technology characterization for design

• Adapted from Prof. B. Murmann (Stanford) notes

3

• VT Dependency on W

• Gate-controlled depletion region extends in part outside the gate width

• VT monotonically increases with decreasing channel width

4

W W

C WqNV

VVV

T

ox

TA T

TTwideT

2 π

=∆

∆+=

L=0.6u

L=4u

W

[Pierret]

• VT Dependency on L

• Source and drain assist in forming the depletion region under the gate

• With simple model, VT monotonically decreases with decreasing channel length

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  

   

 −+−=∆

∆+=

121 j

Tj

ox

TA T

TTlongT

r W

L r

C WqNV

VVV

W=50u

W=1.5u

[Pierret]

• Temperature Dependence

• Transistor mobility and threshold voltage are dependent on temperature • Mobility ∝T-3/2 due to increased scattering • Threshold voltage decreases with

temperature due to reduced bandgap energy

6

23

0 300

  

  =

T µµ

W=2.4u, L=0.6u

ID vs Temperature

W=2.4u, L=0.6u

VT vs Temperature

1108 1002.716.1

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+ ×

−= −

T TEg

-23% -3%

• Process Corners

• Substantial process variations can exist from wafer to wafer and lot to lot

• Device characteristics are guaranteed to lie in a performance envelope

• To guarantee circuit yield, designers simulate over the “corners” of this envelope

• Example: Slow Corner • Thicker oxide (high VT, low Cox), low µ, high R�

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FF

FS

SF

SS

TT

[Razavi]

• Inverter Delay Variation with Process & Temperature

8

0.13µm CMOS

• CMOS inverter delay varies close to ±40% over process and temperature

[Woo ISSCC 2009]

• How to Design with Modern Sub-Micron (Nanometer) Transistors? • Hand calculations with square-law model can deviate

significantly from actual device performance • However, advanced model equations are too tedious for design

• Tempts designers to dive straight to simulation with little understanding on circuit performance trade-offs • “Spice Monkey” approach

• How can we accurately design when hand analysis models are way off?

• Employ a design methodology which leverages characterization data from BSIM simulations

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• The Problem

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[Murmann]

• The Solution

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[Murmann]

• Device Figures of Merit

• Transconductance efficiency • Want maximum gm for minimum current

• Transit frequency, fT • Want maximum gm for minimum Cgg • Cgg = total gate cap = Cgs + Cgd +Cgb

• Intrinsic gain • Want maximum gm/gds

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D

m

I g

gg

m T C

g =ω

ds

m

g g

TGSOV

OV

VVV V

−=

= 2

only assuming gsgg

OV

CC L V

=

≅ 22 3 µ

OVVλ 2

Square-Law

• Technology Characterization for Design

• Generate data for the following over a reasonable range of gm/ID and channel lengths • Transit frequency (fT) • Intrinsic gain (gm/gds) • Current density (ID/W)

• Also useful is extrinsic capacitor ratios • Cgd/Cgg and Cdd/Cgg

• Parameters are (to first order) independent of transistor width, which enables “normalized design”

• Do design hand calculations using the generated technology data

• Still need to understand how the circuit operates for an efficient design!!!

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• Our 0.6um Technology Simulation Data

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NMOS W=2.4um

• Our 0.6um Technology Simulation Data

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NMOS W=2.4um

• Next Time

• Layout Techniques

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ECEN474: (Analog) VLSI Circuit Design Fall 2010 Announcements Agenda VT Dependency on W VT Dependency on L Temperature Dependence Process Corners Inverter Delay Variation with �Process & Temperature How to Design with Modern Sub-Micron (Nanometer) Transistors? The Problem The Solution Device Figures of Merit Technology Characterization for Design Our 0.6um Technology Simulation Data Our 0.6um Technology Simulation Data Next Time

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