ECEN474/704: (Analog) VLSI Circuit Design Spring 2016spalermo/ecen474/lecture14_ee474_miller_ota.pdf · ECEN474/704: (Analog) VLSI Circuit Design Spring 2016. Announcements & Agenda

Sam PalermoAnalog & Mixed-Signal Center

Texas A&M University

Lecture 14: Two Stage Miller OTA

ECEN474/704: (Analog) VLSI Circuit Design Spring 2016

Announcements & Agenda

• HW5 (Preliminary Project Report) Due Apr. 18

• Two Stage Miller OTA• OpAmp Characterization

2

Multi-Stage Amplifiers

3

• Single-stage amplifiers typically have to trade-off gain and swing range

• Multi-stage amplifiers allow for higher gain without sacrificing swing range

• The major challenge with multi-stage amplifiers is achieving adequate phase margin to insure stability in a feedback configuration

Two Stage Miller OTA

4

42

2818

78

7842

82

78

8

42

221

1

oo

mmvmm

ooout

outmVDC

oooo

mm

oo

m

oo

mvvVDC

ggggAgG

ggR

RGAgggg

gggg

ggg

gAAA

Gain DC

Two-Stage Miller OTA – Frequency Response

5

• Stage 1 is a differential amplifier with an active load

• Stage 2 is a common-source amplifier with a large miller capacitor

• Using a Thevenin equivalent for Stage 1, we can use the common-source equations from Lecture 8

Two-Stage Miller OTA – Frequency Response

6

• The amplifier should be designed to yield one dominant pole, so we use the dominant pole approximation equations

872421

8

21

22812

28122811

and where

1

11

1esCapacitancTransistorNeglecting

OOoutOOout

L

m

LCoutout

LCoutCoutmoutp

CoutmoutLCoutCoutmoutp

rrRrrRCg

CCRRCCRCRgR

CRgRCCRCRgR

Jose Silva-Martinez -7- Texas A&M University

ELEN-474

VSS

M1 M1

01i 01i

-vd

01iM2 M2

02iM3

012i

vd

R1 C1RL CL

-v0

VDD

2

1

1

1

21

2

1

11

3

1

1

tantan180arg_

,min*

p

u

p

u

ppVDC

L

Lp

p

L

mmVDC

inmPhase

AGBWCgCg

gg

ggA

valid?) system, poledominant (if

(LHP)

(LHP)

Main equations

p1 p2 GBW

AVDCPhase Margin < 45 degrees

Phase

u

21

11pp

VDC

ssAsA

Frequency Response – No Compensation

TAMU-Elen-474 Jose Silva-Martinez-08

- 8 -

VSS

M1 M1

01i 01i

-vd

01iM2 M2

02iM3

012i

vd

R1 C1 CMRL CL

-v0

VDD

Phase compensation Pole splitting techniques!!

p1 p2

GBW

AVDC

After compensation Phase Margin > 45 degrees Bandwidth is reduced!!!

p1’

p2’u

2

1

1

1

11

1

32

31

11

3

1

1

tantan180arg_

*

pp

M

mpVDC

L

mp

ML

mp

L

mmVDC

WGBWGBinmPhase

CgAWGB

CCg

CggC

ggg

ggA

(LHP)

(LHP)

Frequency Response – Miller Compensation (Ignoring z)


- 9 -

ZEROpp

M

mpVDC

L

mp

ML

mp

L

mmVDC

WGBWGBWGBinmPhase

CgAWGB

CCg

CggC

ggg

ggA

1

2

1

1

1

11

1

32

31

11

3

1

1

tantantan180arg_

*

(LHP)

(LHP)

VSS

M1 M1

01i 01i

-vd

01iM2 M2

02iM3

012i

vd

R1 C1 CMRL CL

-v0

VDD

Parasitic (bad) RHP zero!!

p1 p2

GBW

AVDC

After compensation Phase Margin > 45 degrees Bandwidth is reduced!!!

p1’

GBW’ZER

O

(RHP) M

mZERO C

g 3

p2’

21

11

1

pp

zVDC

ss

sAsA

Frequency Response – Miller Compensation (Considering z)


- 10 -

VSS

M1 M1

01i 01i

-vd

01iM2 M2

02iM3

012i

vd

R1 C1 CMRL CL

-v0

VDD

ZERO

u1

2p

u1

1p

u1 tan'

tan'

tan180inargm_Phase

Parasitic (bad) RHP zero!! Can be catastrophic if close or below wu!

p1 p2

GBW

AVDC After compensation Phase Margin > 45 degrees Bandwidth is reduced!!!

p1’

GBW’ZER

O

M

3mZERO C

g

p2’

p1 p2

GBW

AVDC

After compensation Phase Margin << 45 degrees Phase is equivalent to having 3 poles below unity gain frequency Unstable!

p1’

uZERO

p2’

z Impact on Frequency Response


- 11 -

VSS

M1 M1

01i 01i

-vd

01iM2 M2

02iM3

012i

vd

R1 C1 CMRL CL

-v0

VDD

M4VBIB1

IB2

Adding a series resistance

RZ

321

111

1

ppp

zVDC

sss

sAsA

13

1CRZ

p

MZm

z

CRg

3

11

(Generally high frequency & can be ignored)

p2

Z

Z

cancel can

LFP to RHP from zero pushes

infinity to zero RHP the pushes

)(initially frequencyhigher a to RHP push will R zero-Nonmargin phase improve to R design Can

Mm

MLZ

mZ

mZ

CgCCCR

gR

gR

3

1

3

3

1

1

Two Stage Miller OTA Noise

12

2

42

82

784

22

22

2

42

84

2

42

8278

2

22381

PSD Voltage Noise Referred-Input

223

8

PSDCurrent NoiseReferred-Output

oo

mm

mmm

mm

oi

oo

mm

oo

mmmm

o

gggg

ggggkT

Gfi

fv

gggg

ggggggkT

fi


ELEN-474

OPAMP Characterization

Main parameters to be measured:

•DC gain (104-106) V/V)•Frequency Limitations

•Bandwith (Few Hertz~1kHz)•Gain-Bandwidth product (1~100 Mhz)

•Output resistance •Input Impedance•Signal Swing

•Common-mode input range•Output swing

•Stability•DC Offset•Slew-rate•CMRR•PSRR

For this section, see: CMOS Analog design, Allen & Holberg2nd edition, HPR, 2002.


ELEN-474


DC gain (104-106) V/V) :

•Very difficult to measure in open-loop due to DC offsets.

+

-V00

How to measure/characterize it?

•Stabilize for DC

•For DC, the OPAMP operates in closed loop!!•For frequencies higher than 1/RCCC, the OPAMP operates in open-loop with a grounded load given by RC.

+

-V0

RCCC

Vi


ELEN-474

OPAMP: DC CharacterizationHow to measure/characterize it?

•At DC

•If A(s)B(s) <<1 then the measured gain is dominated by the OPAMP transfer function!

+

-V0

RCCC

Vi

CC

CC

C

i

o

CsR11

sC1R

sC1

)s(B

)s(B)s(A1)s(A

vv

A(s)

)s(Avv

1)s(A1

)s(Avv

i

o

i

o

AVDC

P1GBW

OPAMP (open-loop)

CCDC1P CR

1A

CCCR1

Make sure to set RCCCsuch that


ELEN-474


DC Offset

+

-V0~VoffsetA(s)

Voffset


ELEN-474

OPAMP Characterization: GBW and stability

+

-V0A(s)

Vin

AVDC

P1

GBW

OPAMP (open-loop)

+

-V0A(s)

Vin

t

Vi

Enough phase margin


ELEN-474

OPAMP Characterization: GBW and stability

+

-V0A(s)

Vin

AVDC

P1

OPAMP (open-loop)

+

-V0A(s)

Vin

t

Vi

Not enough phase margin


ELEN-474

OPAMP Characterization: Slew-Rate (max speed)

+

-V0A(s)

Vin

t

VSS

VDD

Slew-Rate

)t(Vodtdmax

Min output level

Max output level


ELEN-474

OPAMP Characterization: Output Swing

+

-A(s)

Vin

t

Vmin

Vmax

Low-Frequency Gain

DC Offset

ifreqlow V

VoA

vivo

Use a slow triangular input signal such that the raising and falling edges are not determined by slew rate limitations

Output swing

vi

vo

Small signal (~ 10 mV)


ELEN-474

OPAMP Characterization: Input and Output impedance

+

-A(s)Vin

iin

R

CRC

Zin

+

-

RCCC

A(s)

Vin

iin

RC and CC as large as possible!!

At Low frequencies:Zmeasured Zo (Why????)

At medium frequencies: Zmeasured = Zo||RC

Be sure that the OPAMP (all internal transistors) is properly biased during characterization!!

Next Time

• OpAmp Feedback & Stability• Common-Mode Feedback Techniques

22

Documents

ECEN474/704: (Analog) VLSI Circuit Design Spring 2016spalermo/ecen474/lecture14_ee474_miller_ota.pdf · ECEN474/704: (Analog) VLSI Circuit Design Spring 2016. Announcements & Agenda