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  • Sam Palermo Analog & Mixed-Signal Center

    Texas A&M University

    Lecture 13: Folded Cascode & Two Stage Miller OTA

    ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

  • Announcements

    • Exam dates reminder • Exam 2 is on Apr. 10 • Exam 3 is on May 3 (3PM-5PM)

    • Project description is posted on website

    2

  • Agenda

    • Single-Stage Cascode OTA

    • Folded Cascode OTA

    • Two Stage Miller OTA

    3

  • Simple OTA

    4

    M1 M2Vi+ Vi-

    VDD

    VSS

    Rbias

    Itail

    M5 M6

    M3 M4

    CL

    Vo

     621 || oomoutmv rrgRGA  Gain DC

    • Gain is limited by single-transistor output resistance

  • Single-Stage Cascode OTA

    • Gain is larger by a gmro factor • Output swing range is limited

    due to large compliance voltage of cascode current source load

    5

     6864241 || oomoommoutmv rrgrrggRGA  Gain DC [Razavi]

  • Single-Stage Cascode OTA Unity Gain Feedback Voltage Range

    6

       

    !!! a than Less Range Input) (&Output

    conditionsat M2 into plugging and As

    saturation M2by set V Maximum

    saturationM4by set V Minimum

    244

    24242

    4

    2

    out

    4

    out

    TH

    THGSTH

    THGSbTHGSbTHxout

    xGSxb

    THxout

    THbout

    V VVV

    VVVVVVVVV VVVV VVV

    VVV

     

     

    

    • Cascode configuration constrains output & unity-gain swing

    [Razavi]

  • Folded Cascode Circuits

    7

    • “Folding” about the cascode node will increase input and output swing range

    PMOS Input & NMOS Cascode

    NMOS Input & PMOS Cascode

    [Razavi]

  • Folded Cascode OTA

    8

    [Razavi]

  • Folded Cascode OTA Unity Gain Feedback Voltage Range

    9

    • With proper (high-value) choice of Vb2, a decent output and input swing range can be achieved

    1

    2 ||

    GSDSATIoutDSATNDSATNCout

    THPbout

    VVVVVV

    VVV MP

    Tail 

    

    OR saturation sourcecurrent tailor cascode NMOSoutput byset V Minimum

    saturation byset V Maximum

    out

    out

    MP

    MNC

  • TAMU-ELEN-474 2009 Jose Silva-Martinez

    - 10 -

    Folded-Cascode OTA: gm, rout and poles?

    VB1 and VB2 must keep M1

    - M5 in saturation region

    VB2 > Vsat,4 + VGS3

    VB1 < VDD - Vsat,5 – VSG2

    Notice that ID5 biases both M2 and M1

        43351221 ; dsmdsdsdsmdsoutmm rgrrrgrrgG 

    (for M4 sat)

    (for M5 sat)

  • TAMU-ELEN-474 2009 Jose Silva-Martinez

    - 11 -

    Example: Folded-Cascode OPAMP

    Find the gain and the phase from input to output and from input to node 2.

    The low frequency gain is 77 dB and the unity gain frequency is around 80 MHz. The behavior of the gain from the input to node 2 is interesting: above the dominant pole.

    51

    1

    oo

    m

    gg g 

     2

    1

    m

    m

    g g

     

      

      

      

     

     Loutoo

    m z Crgg

    g 1

    51

    2 2

  • TAMU-Elen-474 Jose Silva-Martinez-08

    - 12 -

    FOLDED-CASCODE OTA Frequency response:

    Can be approximated as having 4 poles associated

    with nodes Vout, VX/W, VZ, and VY

    The poles at Vy and Vz are associated to

    N-type transistors higher frequencies

     

    mnc

    Z

    mn

    Y

    mp

    PC

    out

    out outmV

    g sC

    g sC

    g sC

    g sCRgsA 

     

     

     

     1

    1

    1

    1

    1

    1

    1

    1 1

    vin-

    2ID1

    M1

    MP

    vout

    VB2

    VB1 vin+

    2ID1

    VB2 iOUT1

    2ID1

    VDD

    -VSSMN

    VB3

    MN

    VB1

    VWVX

    VY

    VZ

  • TAMU-Elen-474 Jose Silva-Martinez-08

    - 13 -

    Output referred noise M1 produces an output current given by

    Each transistor M2 generates a differential output current

    Similarly, for each transistor M5

    At low and medium frequencies, noise contribution of the cascode transistors can be neglected (M3 and M4)

    Vn4

    ro5

    i04

    M4 05

    4n 4n

    054m

    4m 04 r

    v v

    rg1 g

    i  

    For cascode transistors

    1n1m01 vgi 

    2n2m02 vgi 

    5n5m05 vgi 

    vin-

    2ID1

    M1

    M2

    vout

    VB2

    VB1 vin+

    2ID1

    VB2 iOUT1

    2ID1

    VDD

    -VSSMN

    VB3

    MN

    VB1

    VW VX

    VY

    VZ M4

    M5

    M3

    iout2 = 2(ieq12 + ieq22 + ieqn2 )

    meq kTgi 3 82 Remember

     mnmmout gggkTf i

      21 2

    3 16

  • TAMU-Elen-474 Jose Silva-Martinez-08

    - 14 -

    Noise level for the folded-cascode OTA

    Let’s find the input rms noise

    Low-noise is associated with large gm1 and relatively small gm2 and gm5

      

      

     

    BW m

    m

    m

    m

    m noise dfg

    g g g

    g kTv 2

    1

    5 2

    1

    2

    1

    1 3

    16

       

       

     

     

       

     

    1

    5

    1

    2

    1

    18

    m

    m

    m

    m

    m noise g

    g g gBW

    g kTv

    Or for a dominant (single) pole system with NBW = (/2)BW

    vin-

    2ID1

    M1

    M2

    vout

    VB2

    VB1 vin+

    2ID1

    VB2 iOUT1

    2ID1

    VDD

    -VSSM5

    VB3

    M5

    VB1

    VW VX

    VY

    VZ

    Noise of diff pair Noise Factor (due to other transistors)

       

      

     

      

      

      

     

      21

    212

    22 1 3

    161

    m mnmm

    m

    outin

    g gggkT

    Gf i

    f v

    Considering thermal noise only

  • Multi-Stage Amplifiers

    15

    • Single-stage amplifiers typically have to trade-off gain and swing range

    • Multi-stage amplifiers allow for higher gain without sacrificing swing range

    • The major challenge with multi-stage amplifiers is achieving adequate phase margin to insure stability in a feedback configuration

  • Two Stage Miller OTA

    16

      

    42

    28 18

    78

    7842

    82

    78

    8

    42

    2 21

    1

    oo

    mm vmm

    oo out

    outmVDC

    oooo

    mm

    oo

    m

    oo

    m vvVDC

    gg ggAgG

    gg R

    RGA gggg

    gg gg

    g gg

    gAAA

     

     

     

      

     

     

      

     

     Gain DC

  • Two-Stage Miller OTA – Frequency Response

    17

    • Stage 1 is a differential amplifier with an active load

    • Stage 2 is a common-source amplifier with a large miller capacitor

    • Using a Thevenin equivalent for Stage 1, we can use the common-source equations from Lecture 8

  • Two-Stage Miller OTA – Frequency Response

    18

    • The amplifier should be designed to yield one dominant pole, so we use the dominant pole approximation equations

           

    872421

    8

    21

    2281 2

    2812281 1

    and where

    1

    1 1

    1 esCapacitancTransistorNeglecting

    OOoutOOout

    L

    m

    LCoutout

    LCoutCoutmout p

    CoutmoutLCoutCoutmout p

    rrRrrR C g

    CCRR CCRCRgR

    CRgRCCRCRgR

    

     

     

  • Jose Silva-Martinez -19- Texas A&M University

    ELEN-474

    VSS

    M1 M1

    01i 01i

    -vd

    01i M2 M2

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