ECEN474/704: (Analog) VLSI Circuit Design Spring 2016 2018. 9. 10.¢  ECEN474/704: (Analog) VLSI Circuit

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  • Sam Palermo Analog & Mixed-Signal Center

    Texas A&M University

    Lecture 2: MOS Transistor Modeling

    ECEN474/704: (Analog) VLSI Circuit Design Spring 2016

  • Announcements

    • Turn in your 0.18um NDA form and email me your linux username

    • No Lab this week • Lab 1 starts Feb 2 or 3

    • Current Reading • Razavi Chapters 2 & 16

    2

  • Agenda

    • MOS Transistor Modeling • Threshold Voltage, VT • DC I-V Equations • Body Effect • Subthreshold Region

    3

  • Threshold Voltage, VT

    • Before a “channel” forms, the device acts as 2 series caps from the oxide cap and the depletion cap

    • If VG is increased to a sufficient value the area below the gate is “inverted” and electrons flow from source to drain

    4

    [Razavi]

    • Applying a positive voltage to the gate repels holes in the p-substrate under the gate, leaving negative ions (depletion region) to mirror the gate charge

  • ox

    ox oxox

    subFsidepdep

    i

    sub FF

    MS

    FFMS ox

    dep FMST

    t CC

    NqQQ

    n N

    q kT

    C Q

    V

    

     

      

     

    

    cap/area, gate theis

    4 charge,region depletion theis

    ln potential, Fermi theis

    substratesilicon theand gaten polysilico theof functions work ebetween th difference theis

    222

    VT Definition

    • The threshold voltage, VT, is the voltage at which an “inversion layer” is formed • For an NMOS this is when the

    concentration of electrons equals the concentration of holes in the p- substrate

    5

    [Silva]

    Note,  will be defined later

  • - 6 -

    TAMU-474-09 J. Silva-Martinez

    MOS Transistor

    substrate

    N+ N+

    VS=0 VG0

    P

    P+

    B D

    S

    B G

    N-type transistor

    + + + + + + + + + +

    Accumulation: Two diodes back to back D-S current is zero

    P+

    Substrate

    N+ N+

    VS=0 VG>0

    VD>0

    P

    P+

    B

    - - - - - - - - - -

    Inversion: Channel is connecting D and S D-S current is possible

    IDS

    Under this condition, there are 3 possible applications:

    Subthreshold (extremely low-voltage low- power applications)

    Linear region (voltage controlled resistor, linear OTA’s, multipliers, switches)

    Saturation region (Amplifiers) Quasi free electrons N+

  • - 7 -

    TAMU-474-09 J. Silva-Martinez

    MOS Transistor

    D

    S

    B G

    N-type transistorTriode Region (D-S channel is complete)

    In this condition, there are 3 possible applications:

    Subthreshold (extremely low-voltage low- power applications)

    Linear region (voltage controlled resistor, linear OTA’s, multipliers, switches)

    Saturation region (Amplifiers)

    substrate

    N+ N+

    VS=0 VG>0

    VD ~ 0

    P

    P+

    B

    - - - - - - - - - -

    Channel

    substrate

    N+ N+

    VS=0 VG>0

    VD > 0

    P

    P+

    B

    Saturation Region (D-S channel is incomplete)

    N-channel

  • - 8 -

    TAMU-474-09 J. Silva-Martinez

    MOS Transistor

    N-type transistor

    substrate

    N+ N+

    VS=0 VT >VG>0 VD>0

    P (NA)

    P+

    B

    Subthreshold (weak inversion)

    Mobile carriers concentration< NA

    - - - - - - - -

    substrate

    N+ N+

    VS=0 VG>VT VD>0

    P (NA)

    P+

    B

    Saturation (Strong inversion)

    Mobile carriers Concentration> NA

    - - - - - - - -

    Subthreshold

    Linear region

    Saturation

    VD S

    IDS

    Subthreshold (extremely low-voltage low- power applications)

    Linear region (voltage controlled resistor, linear OTA’s, multipliers, switches)

    Saturation region (Amplifiers)

    VGS2

    VGS3

    VGS1

  • MOS Equations in Triode Region (Small VDS)

    9

    [Sedra/Smith]

     

     

       

     

     

    DSDSTGSOXnDS

    V

    CSTGSOXn

    L

    DS

    nTCSGSOXDS

    nn

    TCSGSTGC

    TGCOXd

    d

    VVVV L WCI

    xdvxVVVWCdxI

    dx xdvVxVVWCII

    dx xdvxE

    VxVVVxV

    VxVWCxQ

    xQ dt dx

    dx dQ

    dt dQI

    DS

      

       

    

    

    

    

    

    

    

    2 1

    ))((

    ))((

    :VelocityElectron

    )( :Voltage Channel-to-Gate

    )()( :Density Charge lIncrementa

    )( :Drain toSource fromCurrent

    00

    

    DSII 

    n :mobilityElectron

    :area gateunit per eCapacitanc

    ox

    ox ox t

    C 

  • Triode or Linear Region

    • Channel depth and transistor current is a function of the overdrive voltage, VGS-VT, and VDS

    • Because VDS is small, VGC is roughly constant across channel length and channel depth is roughly uniform

    10

    x=0 x=L

    VDS

      DSDSTnGSOXnDS VVVVCL WI 5.0 

      00 V   DSVLV   L xVxV DS

        L xVVxVVxV DSGSGSGC 

     TnGSox DS

    VVC L WR

     

    1

    For small VDS

    [Silva]

  • - 11 -

    TAMU-474-09 J. Silva-Martinez

    MOS Equations in Linear Region

    L

    W

    tox

    N+ N+

    VDSGND VGS

    Drain current: Expression used in SPICE level 1

      DSDSTGSOXnD VV5.0VVCL WI 

    W

    tox

    N+ N+

    VDSGND VGS

    Non-linear channel

    Linear approximation

    VDS

    ID

    VOV=VGS-VT

    IDSAT

    VGS > VT

    • This expression peaks when VDS=VGS-VT, which we will call the “overdrive voltage” or VOV

  • Triode Region Channel Profile

    12

    [Sedra/Smith]

    • If VGC is always above VT throughout the channel length, the transistor current obeys the triode region current equation

    • Recall that the channel charge density is (VGC(x) - VT)

    Channel Voltage, V(x)

        L xVVVxVVVxV DSOVTGSTGC 

  • Saturation Region Channel Profile

    13

    [Sedra/Smith]

    • When VDS  VGS-VT=VOV, VGC no longer exceeds VT, resulting in the channel “pinching off” and the current saturating to a value that is no longer a function of VDS (ideally)

        L xVVVxVVVxV DSOVTGSTGC 

    Channel Voltage, V(x)

  •     L xVVVxVVVxV DSOVTGSTGC 

    Saturation Region

    • Channel “pinches-off” when VDS=VGS-VT and the current saturates • After channel charge goes to 0, the high lateral field “sweeps” the

    carriers to the drain and drops the extra VDS voltage

    14

    x=0 x=L

    VDSsat=VGS-VT

      00 V   DSVLV   L xVxV DS

    VDS-VDSsat

    TnGSOV VVV 

    [Silva]

     2 2 TnGS

    OXn DS VVL

    WCI  

     2 2 TnGSOXnVVV

    DS DS

    TnGSOXnDS VVL WCVVVV

    L WCI

    TnGSDS

      

        

     

    

    x=L’

  • NMOS ID – VDS Characteristics

    15

    TNGSOV VVV  [Sedra/Smith]

  • MOS “Large-Signal” Output Characteristic

    16

    [Sedra/Smith]

    Note: Vov=VGS-VT

  • What about the PMOS device?

    • The current equations for the PMOS device are the same as the NMOS EXCEPT you swap the current direction and all the voltage polarities

    17

      DSDSTnGSOXnDS VVVVCL WI 5.0    SDSDTpSGOXpSD VVVVCL

    WI 5.0 

     2 2 TnGSOXnDS

    VVC L

    WI    2 2 TpSGOXpSD

    VVC L

    WI  

    Linear:

    Saturation:

    NMOS PMOS

    NMOS PMOS

    [Silva]

  • PMOS ID – VSD Characteristics

    18

    [Karsilayan]

    (Saturation)

    TPSGOV VVV 

  • Body Effect

    • As VS becomes positive w.r.t. VB, a larger depletion region forms, which requires a higher VG to form a channel

    • The net result is that VT increases due to this “body effect”

    • Note, it also works in reverse,

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