Analog VLSI systems - UPBcsit-sun.pub.ro/courses/vlsi/VLSI_Darmstad/... · Analog VLSI systems 21.1 Analog Signal Processing Typical signal processing applications require mixed analog/digital

Analog Signal Processing

Chapter 21

Analog VLSI systems

21.1 Analog Signal Processing

Typical signal processing applications require mixed analog/digital implementations. Thesemainly consist of

• Preprocessing of the signals, e.g. filtering and A/D conversion

• Digital signal processing, e.g. digital filtering, calculation of FFT

• Postprocessing, e.g. D/A conversion

as shown in Fig.21.1

The aim of development is to integrate all these functions on a single chip.

Figure 21.1: Block diagram of a typical signal processing system

VLSI DesignCourse 21-1

Darmstadt University of TechnologyInstitute of Microelectronic Systems 0


21.1.1 Signal Bandwidths in Analog VLSI

Figure 21.2: Bandwidths of signals used in signal processing applications

Figure 21.3: Signal bandwidths that can be processed by present day (1989)technologies




21.1.2 A/D and D/A Conversion in Signal Processing Systems

Fig. 21.4 illustrates how analog-to-digital (A/D) and digital-to-analog (D/A) converters areused in data systems. In general, an A/D conversion process will convert a sampled andheld analog signal to a digital word that is a representative of the analog signal. The D/Aconversion process is essentially the inverse of the A/D process. Digital words are applied tothe input of the D/A converter to create from a reference voltage an analog output signal thatis a representative of the digital word.

Figure 21.4: Converters in signal processing systems: (a) A/D, (b) D/A



Digital-To-Analog Converters

21.2 Digital-To-Analog Converters

Input to D/A converters are

(a) a digital word of N bits (b1, b2, b3, . . . , bN )

(b) a reference Voltage Vref

The output voltage can be expressed as

VOUT = KVrefD (21.1)

where K is a scaling factor and D is given as

D =b121

+b222

+b323

+ . . .+bN2N

(21.2)

Thus, the output of a D/A converter can be expressed by

VOUT = KVref

N∑i=1

bi2−i (21.3)

Figure 21.5: (a) Conceptual block diagram of a D/A converter, (b) ClockedD/A converter

In most cases, the digital input of the D/A converter is synchronously clocked. It is thereforenecessary to provide a latch to hold the word for conversion and a sample-and-hold circuit atthe output, as shown in Fig. 21.5(b).

The basic architecture of the D/A converter without an output sample-and-hold circuit isshown in Fig. 21.7. Fig. 21.8 shows the ideal input-output characteristics for such a D/Aconverter.

21.2.1 Current Scaling D/A Converters

The output Voltage of a current-scaling D/A converter as shown in Fig. 21.9 can be expressedas

Vout = −R2I0 = −R

2

(b1R

+b22R

+b34R

+ . . .+bN

2N−1R

)Vref (21.4)

= −Vref (b12−1 + b22−2 + b32−3 + . . .+ bN2−N ) (21.5)




Figure 21.6: (a) Sample-and-hold circuit, (b) Waveforms illustrating the op-eration of the sample-and-hold circuit

Figure 21.7: Block diagram of a D/A converter




Figure 21.8: Ideal input-output characteristics for a 3-bit D/A converter

The major disadvantage of this approach is the large ratio of component values. For example,the ratio of the resistor for the MSB to the resistor for the LSB is given by

RMSB

RLSB=

12N−1

(21.6)

For a 8-bit converter, this gives a ratio of 1/128.

An alternative to this approach is the use of a R-2R ladder as shown in Fig. 21.10. Using thefact that the resistance to the right of any of the vertical 2R resistors is 2R, we see that thecurrents I1, I2, I3, . . . , IN are binary-weighted and given as

I1 = 2I2 = 4I3 = . . . = 2N−1IN (21.7)

Thus, the output voltage of the R-2R D/A converter is given by Eq. 21.5.




Figure 21.9: (a) Conceptual illustration of a current-scaling D/A converter,(b) Implementation of (a)

Figure 21.10: A current-scaling D/A converter using an R-2R ladder




21.2.2 Voltage Scaling D/A Converters

A voltage-scaling D/A converter is shown in Fig. 21.11. Its output voltage at any tap i canbe expressed as

Vi =Vref

8(i− 0.5) (21.8)

The output voltage of the D/A converter is then determined by the values of the inputs b1,b2 and b3.

Figure 21.11: Illustration of a voltage-scaling D/A converter

The structure of this voltage-scaling D/A converter is very regular and thus well suited forMOS technology. A problem with this type of D/A converters is the accuracy requirementsof the resistors used. This makes it difficult to build D/A converters of this type with morethan 8 bit resolution.



Analog-To-Digital Converters

21.3 Analog-To-Digital Converters

The objective of an A/D converter is the determination of the digital word corresponding tothe analog input signal. Usually a sample-and-hold circuit (see Fig. 21.6) is required at theinput of the A/D converter because it is not possible to convert a changing analog signal. Ablock diagram of a general A/D converter is shown in Fig. 21.12. The ideal input-outputcharacteristics for a A/D converter are shown in Fig. 21.13.

Figure 21.12: Block diagram of a general analog-to-digital converter

Figure 21.13: Ideal input-output characteristics for a 3-bit A/D converter




21.3.1 Serial A/D Converters

Two possible implementations of serial A/D converters are single-slope and dual-slope A/Dconverters. Both will not be discussed in detail here. The main advantages of these convertersis their simplicity, their main disadvantage is the long conversion time required.

21.3.2 Successive Approximation A/D Converters

This type of A/D converters converts an analog input into an N-bit digital word in N clockcycles. Consequently, the conversion time is less than for the serial converters without muchincrease in the complexity of the circuit. Fig. 21.14 shows an example of a successive approx-imation A/D converter architecture.

Figure 21.14: Example of a successive approximation A/D converter archi-tecture

The successive approximation process is shown in Fig. 21.15.




Figure 21.15: The successive approximation process

21.3.3 Parallel A/D Converters

In many applications, it is necessary to have a smaller conversion time than is possible withthe previously described A/D converter architectures. Parallel A/D converters, also known asflash A/D converters, typically require down to one clock cycle for conversion. An architectureof a 3-bit parallel A/D converter is shown in Fig. 21.16.

Parallel A/D converters can reach typically up to 20 MHz for CMOS technology. The sample-and-hold time may though be larger than 50 ns and could prevent this conversion time frombeing realised. Another problem is that the number of comparators required is 2N−1. For Ngreater than 8, too much area is required.

One method of achieving small system conversion times is to use slower A/D converters inparallel, which is called time-interleaving and is shown in Fig. 21.17. Here M successiveapproximation A/D converters are used in parallel to complete the N -bit conversion of oneanalog signal per clock cycle. The sample-and-hold circuits consecutively sample and applythe input analog signal to their respective A/D converters. N clock cycles later, the A/Dconverter provides a digital word output. If M = N , then a digital word is given out everyclock cycle. If one examines the chip area for an N -bit A/D converter using the parallel A/Dconverter architecture (M = 1) compared with the time-interleaved architecture for M = N ,the minimum area will occur for a value of M between 1 and N .




Figure 21.16: A 3-bit parallel A/D converter




Figure 21.17: A time-interleaved A/D converter array




21.3.4 Sigma-Delta A/D Converter

Introduction

The basic structure of a sigma-delta converter is shown in Fig. 21.18. The sigma-delta con-verter can be referred to as an oversampling converter, although oversampling is just one ofthe techniques contributing to the performance of a sigma-delta converter. The sigma-deltaconverter shown in Fig. 21.18 quantizes an analog signal with very low resolution (1 bit) anda very high sampling rate (2 MHz). With the use of oversampling techniques and digitalfiltering, the sampling rate is reduced (8 kHz) and the resolution is increased (16 bits).

Figure 21.18: Basic structure of a sigma-delta converter

A more detailed block diagram of the sigma-delta modulator is shown in Fig. 21.19. It consistsof an integrator, a quantizer (comparator for 1 bit) and a feedback loop with a D/A converter(switch for 1 bit). The output of the sigma-delta modulator is shown in Fig.21.20 for a sinewave input. The single-bit conversion will result in an output which is either ’1’ or ’0’. Whenthe signal is near plus full scale, the output is positive during most of the clock cycles. Theopposite is true for near minus full scale signals. When the output is followed by a digitalfilter as shown in Fig. 21.18 which can perform sophisticated averaging functions, the 1-bitsequence is transformed into a much more meaningful signal.

Figure 21.19: First-order sigma-delta modulator block diagram

Noise Shaping

One feature that makes the sigma-delta converter so powerful is its noise shaping capability.To understand how this works, the analysis of the sigma-delta modulator in the frequencydomain is appropriate. Fig.21.21 shows the frequency domain linearized model of a sigma-delta modulator.




Figure 21.20: Output of first-order sigma-delta modulator

Figure 21.21: Frequency domain linearized model of a sigma-delta modula-tor




The integrator is represented as a analog filter. For an integrator, the transfer function hasan amplitude which is inversly proportional to the input frequency ( 1

f relationship). Thequantizer is modelled as a gain stage followed by the addition of quantization noise.

Thus, the output y of the sigma-delta converter can be expressed by

y = (x− y)1f

+ q (21.9)

where (x − y) is the difference signal from the summing node at the input and q is thequantization noise. Applying some algebraic rearrangement yields

y =x

f− y

f+ q(

1 +1f

)y =

x

f+ q

y =xf

1 + 1f

+q

1 + 1f

y =x

f + 1+

qf

f + 1(21.10)

At a frequency f = 0, the output signal equals x with no noise element q. At higher frequencies,the value of x is reduced and the influence of q increases. In essence, the sigma-delta modulatorhas a low pass effect on the signal and a high pass effect on the noise. As a result of this,the modulator can be thought of as a noise shaping filter where noise in the signal pass bandis reduced and noise energy is pushed into the higher frequency region. The effect of thisprocedure on normally equally distributed (white) quantization noise is shown in Fig. 21.22.

Figure 21.22: Noise-shaping filter function




Digital Filtering

The sigma-delta modulator described so far produces a stream of single-bit digital values ata very high rate. The modulator’s output bit stream is fed into the converter’s digital filter,which performs several different functions. All of these functions, however, are integrated intoa single filter implementation. The functions of the filter are:

• sophisticated averaging (low pass filtering)

• removing high frequency noise (quantization noise)

• reducing sampling rate

The sampling rate reduction is done by averaging over a sample of cycles of the input bitstream and produces an output data stream that is reduced in sampling rate, but increasedin resolution (i.e. number of bits per sample).

Advantages of Sigma-Delta Converters

The advantages of the sigma-delta converter technology are

• Sigma-delta converters are a complete conversion and filtering system, additional digitalfiltering functions may easily be implemented in the digital output filter of the converter

• Very low-cost and high-performance conversion ist possible as the analog part of theconverter is very simple and need not be as accurate as in other A/D converters. Themain part of the converter is the digital filter which can be integrated more easily inMOS technology.

• excellent signal-to-noise performance, therefore high resolution converters possible

• no sample-and-hold circuit preceeding the converter is neccessary as sampling rates arevery high



Documents

Analog VLSI systems - UPBcsit-sun.pub.ro/courses/vlsi/VLSI_Darmstad/... · Analog VLSI systems 21.1 Analog Signal Processing Typical signal processing applications require mixed analog/digital