Analog Signal Processing
Analog VLSI systems
21.1 Analog Signal Processing
Typical signal processing applications require mixed analog/digital implementations. Thesemainly consist of
Preprocessing of the signals, e.g. filtering and A/D conversion
Digital signal processing, e.g. digital filtering, calculation of FFT
Postprocessing, e.g. D/A conversion
as shown in Fig.21.1
The aim of development is to integrate all these functions on a single chip.
Figure 21.1: Block diagram of a typical signal processing system
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Analog Signal Processing
21.1.1 Signal Bandwidths in Analog VLSI
Figure 21.2: Bandwidths of signals used in signal processing applications
Figure 21.3: Signal bandwidths that can be processed by present day (1989)technologies
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Analog Signal Processing
21.1.2 A/D and D/A Conversion in Signal Processing Systems
Fig. 21.4 illustrates how analog-to-digital (A/D) and digital-to-analog (D/A) converters areused in data systems. In general, an A/D conversion process will convert a sampled andheld analog signal to a digital word that is a representative of the analog signal. The D/Aconversion process is essentially the inverse of the A/D process. Digital words are applied tothe input of the D/A converter to create from a reference voltage an analog output signal thatis a representative of the digital word.
Figure 21.4: Converters in signal processing systems: (a) A/D, (b) D/A
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21.2 Digital-To-Analog Converters
Input to D/A converters are
(a) a digital word of N bits (b1, b2, b3, . . . , bN )
(b) a reference Voltage Vref
The output voltage can be expressed as
VOUT = KVrefD (21.1)
where K is a scaling factor and D is given as
+ . . .+bN2N
Thus, the output of a D/A converter can be expressed by
VOUT = KVrefNi=1
Figure 21.5: (a) Conceptual block diagram of a D/A converter, (b) ClockedD/A converter
In most cases, the digital input of the D/A converter is synchronously clocked. It is thereforenecessary to provide a latch to hold the word for conversion and a sample-and-hold circuit atthe output, as shown in Fig. 21.5(b).
The basic architecture of the D/A converter without an output sample-and-hold circuit isshown in Fig. 21.7. Fig. 21.8 shows the ideal input-output characteristics for such a D/Aconverter.
21.2.1 Current Scaling D/A Converters
The output Voltage of a current-scaling D/A converter as shown in Fig. 21.9 can be expressedas
Vout = R
+ . . .+bN
= Vref (b121 + b222 + b323 + . . .+ bN2N ) (21.5)
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Figure 21.6: (a) Sample-and-hold circuit, (b) Waveforms illustrating the op-eration of the sample-and-hold circuit
Figure 21.7: Block diagram of a D/A converter
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Figure 21.8: Ideal input-output characteristics for a 3-bit D/A converter
The major disadvantage of this approach is the large ratio of component values. For example,the ratio of the resistor for the MSB to the resistor for the LSB is given by
For a 8-bit converter, this gives a ratio of 1/128.
An alternative to this approach is the use of a R-2R ladder as shown in Fig. 21.10. Using thefact that the resistance to the right of any of the vertical 2R resistors is 2R, we see that thecurrents I1, I2, I3, . . . , IN are binary-weighted and given as
I1 = 2I2 = 4I3 = . . . = 2N1IN (21.7)
Thus, the output voltage of the R-2R D/A converter is given by Eq. 21.5.
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Figure 21.9: (a) Conceptual illustration of a current-scaling D/A converter,(b) Implementation of (a)
Figure 21.10: A current-scaling D/A converter using an R-2R ladder
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21.2.2 Voltage Scaling D/A Converters
A voltage-scaling D/A converter is shown in Fig. 21.11. Its output voltage at any tap i canbe expressed as
8(i 0.5) (21.8)
The output voltage of the D/A converter is then determined by the values of the inputs b1,b2 and b3.
Figure 21.11: Illustration of a voltage-scaling D/A converter
The structure of this voltage-scaling D/A converter is very regular and thus well suited forMOS technology. A problem with this type of D/A converters is the accuracy requirementsof the resistors used. This makes it difficult to build D/A converters of this type with morethan 8 bit resolution.
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21.3 Analog-To-Digital Converters
The objective of an A/D converter is the determination of the digital word corresponding tothe analog input signal. Usually a sample-and-hold circuit (see Fig. 21.6) is required at theinput of the A/D converter because it is not possible to convert a changing analog signal. Ablock diagram of a general A/D converter is shown in Fig. 21.12. The ideal input-outputcharacteristics for a A/D converter are shown in Fig. 21.13.
Figure 21.12: Block diagram of a general analog-to-digital converter
Figure 21.13: Ideal input-output characteristics for a 3-bit A/D converter
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21.3.1 Serial A/D Converters
Two possible implementations of serial A/D converters are single-slope and dual-slope A/Dconverters. Both will not be discussed in detail here. The main advantages of these convertersis their simplicity, their main disadvantage is the long conversion time required.
21.3.2 Successive Approximation A/D Converters
This type of A/D converters converts an analog input into an N-bit digital word in N clockcycles. Consequently, the conversion time is less than for the serial converters without muchincrease in the complexity of the circuit. Fig. 21.14 shows an example of a successive approx-imation A/D converter architecture.
Figure 21.14: Example of a successive approximation A/D converter archi-tecture
The successive approximation process is shown in Fig. 21.15.
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Figure 21.15: The successive approximation process
21.3.3 Parallel A/D Converters
In many applications, it is necessary to have a smaller conversion time than is possible withthe previously described A/D converter architectures. Parallel A/D converters, also known asflash A/D converters, typically require down to one clock cycle for conversion. An architectureof a 3-bit parallel A/D converter is shown in Fig. 21.16.
Parallel A/D converters can reach typically up to 20 MHz for CMOS technology. The sample-and-hold time may though be larger than 50 ns and could prevent this conversion time frombeing realised. Another problem is that the number of comparators required is 2N1. For Ngreater than 8, too much area is required.
One method of achieving small system conversion times is to use slower A/D converters inparallel, which is called time-interleaving and is shown in Fig. 21.17. Here M successiveapproximation A/D converters are used in parallel to complete the N -bit conversion of oneanalog signal per clock cycle. The sample-and-hold circuits consecutively sample and applythe input analog signal to their respective A/D converters. N clock cycles later, the A/Dconverter provides a digital word output. If M = N , then a digital word is given out everyclock cycle. If one examines the chip area for an N -bit A/D converter using the parallel A/Dconverter architecture (M = 1) compared with the time-interleaved architecture for M = N ,the minimum area will occur for a value of M between 1 and N .
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Figure 21.16: A 3-bit parallel A/D converter
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Figure 21.17: A time-interleaved A/D converter array
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21.3.4 Sigma-Delta A/D Converter
The basic structure of a sigma-delta converter is shown in Fig. 21.18. The sigma-delta con-verter can be referred to as an oversampling converter, although oversampling is just one ofthe techniques contributing to the performance of a sigma-delta converter. The sigma-deltaconverter shown in Fig. 21.18 quantizes an analog signal with very low resolution (1 bit) anda very high sampling rate (2 MHz). With