Lecture 11: Sequential Circuit Design. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits2 Outline  Sequencing  Sequencing Element Design

  • View
    227

  • Download
    8

Embed Size (px)

Text of Lecture 11: Sequential Circuit Design. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential...

  • Slide 1

Lecture 11: Sequential Circuit Design Slide 2 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits2 Outline Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking Slide 3 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Sequential Logic 11: Sequential Circuits3 Slide 4 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits4 Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline Slide 5 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits5 Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high Delay fast tokens so they dont catch slow ones. Slide 6 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits6 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Slide 7 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits7 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, D latch Flip-flop (or Register): edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams Transparent Opaque Edge-trigger Slide 8 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Latch versus Register Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ Slide 9 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Latches 11: Sequential Circuits9 Slide 10 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ Slide 11 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Characterizing Timing 11: Sequential Circuits11 Slide 12 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits12 Latch Design Pass Transistor Latch Pros +Tiny +Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970s Slide 13 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits13 Latch Design Transmission gate +No V t drop - Requires inverted clock Slide 14 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits14 Latch Design Inverting buffer +Restoring +No backdriving +Fixes either Output noise sensitivity Or diffusion input Inverted output Slide 15 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits15 Latch Design Tristate feedback +Static Backdriving risk Static latches are now essential because of leakage Slide 16 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits16 Latch Design Buffered input +Fixes diffusion input +Noninverting Slide 17 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits17 Latch Design Buffered output +No backdriving Widely used in standard cells + Very robust (most important) -Rather large -Rather slow (1.5 2 FO4 delays) -High clock loading Slide 18 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits18 Latch Design Datapath latch +smaller +faster - unbuffered input Slide 19 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits19 Flip-Flop Design Flip-flop is built as pair of back-to-back latches Slide 20 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits20 Enable Enable: ignore clock when en = 0 Mux: increase latch D-Q delay Clock Gating: increase en setup time, skew Slide 21 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits21 Reset Force output low when reset asserted Synchronous vs. asynchronous Slide 22 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits22 Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset Slide 23 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits23 Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches Slide 24 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits24 Timing Diagrams t pd Logic Prop. Delay t cd Logic Cont. Delay t pcq Latch/Flop Clk->Q Prop. Delay t ccq Latch/Flop Clk->Q Cont. Delay t pdq Latch D->Q Prop. Delay t cdq Latch D->Q Cont. Delay t setup Latch/Flop Setup Time t hold Latch/Flop Hold Time Contamination and Propagation Delays Slide 25 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits25 Max-Delay: Flip-Flops Slide 26 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits26 Max Delay: 2-Phase Latches Slide 27 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits27 Max Delay: Pulsed Latches Slide 28 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits28 Min-Delay: Flip-Flops Slide 29 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits29 Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! Slide 30 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits30 Min-Delay: Pulsed Latches Hold time increased by pulse width Slide 31 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Itanium 2 ALU 11: Sequential Circuits31 Slide 32 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Combinational Logic Delays ElementPropagation DelayContamination Delay Adder590 ps100 ps Result Mux60 ps35 ps Early Bypass Mux110 ps95 ps Middle Bypass Mux80 ps55 ps Late Bypass Mux70 ps45 ps 2 mm Wire100 ps65 ps 11: Sequential Circuits32 Slide 33 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits33 Time Borrowing In a flop-based system: Data launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system Data can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle Slide 34 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits34 Time Borrowing Example Slide 35 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits35 How Much Borrowing? 2-Phase Latches Pulsed Latches Slide 36 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits36 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time Decreases maximum propagation delay Increases minimum contamination delay Decreases time borrowing Slide 37 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits37 Skew: Flip-Flops Slide 38 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits38 Skew: Latches 2-Phase Latches Pulsed Latches Slide 39 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits39 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) Slide 40 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits40 Safe Flip-Flop Past years used flip-flop with nonoverlapping clocks Slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk Slide 41 CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits41 Adaptive Sequencing Designers include timing margin Voltage Temperature Process variation Data dependency Tool inaccuracies Alternative: run faster and check for near failures Idea introduced as Razor Increase frequency until at the verge of error Can reduce cycle time by ~30% Slide 42 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Conventional CMOS Latches 11: Sequential Circuits42 Slide 43 CMOS VLSI DesignCMOS VLSI Design 4th Ed. More CMOS Latches 11: Sequential Circuits43 Slide 44 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Clocked CMOS Latches Sometimes called C 2 MOS Actually, similar to (d) in that it is tristate 11: Sequential Circuits44 Slide 45 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Conventional CMOS Flip-Flops 11: Sequential Circuits45 Slide 46 CMOS VLSI DesignCMOS VLSI Design 4th Ed. CMOS Flip-Flops This design has a potential race condition. Is more likely if there is skew between the two phases of the clock. One alternative is NORA (NO Race) flip-flop. The other alternative is to use non-overlapping clocks. 11: Sequential Circuits46 Slide 47 CMOS VLSI DesignCMOS VLSI Design 4th Ed. NORA Flip-flops 11: Sequential Circuits47 Slide 48 CMOS VLSI DesignCMOS VLSI Design 4th Ed. NORA Flip-flops 11: Sequential Circuits48 Slide 49 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pulse Generators 11: Sequential Circuits49 Slide 50 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pulsed Latches The Naffziger pulsed latch is used in Itanium 2 processors. It consists of the latch from (k) and the generator from (b). The pulse width is 1/6 the clock cycle. The pulse generator of (d) is used in the NEC RISC processor. Note that pulses are very fast and have to be distributed in the latch. The Partovi pulsed latch (used on the AMD K6 and Athlon) builds the pulse generator into the latch. 11: Sequential Circuits50 Slide 51 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Pulsed Latches 11: Sequential Circuits51 Slide 52 CMOS VLSI DesignCMOS VLSI Design 4th Ed. Resettable Latches and Flip-flops There are

Search related