S. Reda EN160 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 22: Sequential Circuit Design (1/2)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’08

Sequential circuits

• Purpose of time: we need time to order events• Combinational logic

– output depends on current inputs

• Sequential logic– events are ordered using the clock signal – output depends on current and previous inputs– memory elements are used to store the results of the events

or states (certainly if they will be used in the future).

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs

S. Reda EN160 SP’08

Differences between latches and flipflops

• Latches are level sensitive

• Flipflops are edge triggered

S. Reda EN160 SP’08

Basic latch and bistability requirement

A

C

d

B

Vi2

5V

o1

Vi1 5Vo2

A

C

d

B

Vi2

5V

o1

Vi1 5Vo2

S. Reda EN160 SP’08

1. Latch Design

D Q

• Pass Transistor Latch• Pros

+ Tiny+ Low clock load

• Cons– Vt drop– nonrestoring– output noise sensitivity– dynamic– diffusion input

• Pass Transistor Latch• Pros

++

• Cons

S. Reda EN160 SP’08

1. Latch Design

D Q

• Transmission gate+

-

• Transmission gate+ No Vt drop

- Requires inverted clock

D

XQ

D Q

• Inverting buffer+

+ Fixes either• •

–

• Inverting buffer+ Restoring

+ Fixes either• Output noise sensitivity• Or diffusion input

– Inverted output

S. Reda EN160 SP’08

1. Latch Design

• Tristate feedback+ –

QDX

• Tristate feedback+ Static– Output noise sensitivity– Diffusion input

• Static latches are now essential

QDX

• Buffered input+ Fixes diffusion input

+ Noninverting

- Output noise sensitivity

S. Reda EN160 SP’08

1. Latch Design

Q

D X

• Buffered output+ Output noise sensitivity eliminated

• Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading

Q

D X• Datapath latch

+ Smaller, faster

- unbuffered input

S. Reda EN160 SP’08

2. Flip-flop design

• Flip-flop is built as pair of back-to-back latches

D Q

X

D

X

Q

Q

S. Reda EN160 SP’08

2. Latch/Flip-flop with ENABLE

• Enable: ignore clock when en = 0– Mux: increase latch D-Q delay– Clock Gating: increase in setup time, skew

D Q

Latc

h

D Q

en

en

Latc

hDQ

0

1

en

Latc

h

D Q

en

DQ

0

1

enD Q

en

Flo

p

Flo

p

Flo

p

Symbol Multiplexer Design Clock Gating Design

S. Reda EN160 SP’08

2. Latch/Flip-flop with SET/RESET

• Set forces output high when enabled• Flip-flop with asynchronous set and reset

[Figure from Baker]

S. Reda EN160 SP’08

Setup and hold times

t

CLK

t

D

tc2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q

• Setup time: the minimum time that the data input must be valid before clock transition

• Hold time: the minimum time that the data input must be valid after the clock transition

S. Reda EN160 SP’08

Sequencing timing terminology

tpdLogic Prop. Delay tpdq

Latch D-Q Prop Delay

tcdLogic Cont. Delay tpcq

Latch D-Q Cont. Delay

tpcqLatch/Flop Clk-Q Prop Delay tsetup

Latch/Flop Setup Time

tccqLatch/Flop Clk-Q Cont. Delay thold

Latch/Flop Hold Time