ENG 6090 – VLSI Design Introduction to VLSI Design – Lec01. 1 ENG6090 – VLSI Design Lecture # 1

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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 1 ENG6090 VLSI Design Lecture # 1
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 2 Professor: Shawki Areibi (Off:Thorn 2335) sareibi@uoguelph.ca Lecture Mon - Fri10:30 - 12:00 pm Thorn2336 Laboratory ENG 2307 (Digital Design Lab) Course Web Page www.uoguelph.ca/~sareibi
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 3 Syllabus - VLSI Design/Reconfigurable Computing Grading 30% Assign 10% Presentation 40% Project 20% Exams Texts - Kang & Leblebici. CMOS Digital Integrated Circuits - Rabaey. J. Digital Integrated Circuits, 2002 - Uyemura J. P. Physical Design of CMOS Integrated Circuits Using L-Edit ( optional reference ) Project - Cadence Tools - Technology Files (0.18 process) Course Expectations - Must Do a Project to Illustrate your Understanding COURSE INFORMATION
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 4 1.This course provides an introduction to the fundamental principles of VLSI circuit design. 2.Emphasis is placed on the design of basic building blocks of large scale digital integrated circuits and systems. 3.Understand the concept behind ASIC Design. 4.Implement a complete digital system on silicon using state of the art CAD tools. 5.Understand the consequence of scaling down the dimensions of transistors and its affect on device speed, density, . 6.Have the necessary background to complete CMOS designs and assess which particular design style to use on a given design from FPGA to Full custom design. ENG6090 COURSE OBJECTIVES
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 5 Overview of VLSI Design Cycle and Methodologies nMOS, pMOS transistor theory and design equations Overview of VLSI fabrication technology, Basic CMOS digital circuits, transistor-level and mask-level design, Complex logic gates, modular building blocks Data path components, ASIC design guidelines, Hardware Descriptive Languages Reconfigurable Computing Systems (FPGAs) Physical Design Automation ENG6090 TOPICS TO BE COVERED
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 6 VLSI:Very Large Scale Integration Integration: Integrated Circuits multiple devices on one substrate How large is Very Large? SSI (small scale integration) 7400 series, 10-100 transistors MSI (medium scale) 74000 series 100-1000 LSI 1,000-10,000 transistors VLSI > 10,000 transistors ULSI/SLSI (some disagreement)
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 7 Integration Improves the Design Lower parasitics, higher clocking speed Lower power Physically small Integration Reduces Manufacturing Costs (almost) no manual assembly About $1-5billion/fab Typical Fab 1 city block, a few hundred people Packaging is largest cost Testing is second largest cost For low volume ICs, Design Cost may swamp all manufacturing cost WHY VLSI?
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 8 Specifications IO, Goals and Objectives, Function, Costs Architectural Description VLHD, Verilog, Behavioral, Large Blocks Logic Design Gates plus Registers Circuit Design Transistors sized for power and speed Discrete Logic, Technology Mapping Layout Size, Interconnect, Parasitics Levels of Design
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 9 n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 10 What is CMOS VLSI? MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation) Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate. We call this poly or just red stuff to distinguish it from the body of the chip, the substrate, which is a single crystal of silicon. We do use metal (aluminum) for interconnection wires on the surface of the chip.
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 11 S D G Poly crossed over Diffusion Field effect transistor (FET) Insulated Gate Metal Oxide Semiconductor FET Source and Drain are Interchangeable D S G
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 12 N-Channel Enhancement mode MOS FET Four Terminal Device - substrate bias The self aligned gate - key to CMOS
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 13 CMOS:Complementary MOS Means we are using both N-channel and P-channel type enhancement mode Field Effect Transistors (FETs). Field Effect- NO current from the controlling electrode into the output FET is a voltage controlled current device BJT is a current controlled current device N/P Channel - doping of the substrate for increased carriers (electrons or holes)
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 14 Complementary Metal Oxide Semiconductor PMOS NMOS V SS V DD XX
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 15 Four Views Logic Transistor Layout Physical
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 16 VLSI Design The real issue inVLSI is about designing systems on chips. The designs are complex, and we need to use structured design techniques and sophisticated design tools to manage the complexity of the design. We also accept the fact that any technology we learn the details of will be out of date soon. We are trying to develop and use techniques that will transcend the technology, but still respect it.
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 17 Help from Computer Aided Design tools Tools Editors Simulators Libraries Module Synthesis Place/Route Chip Assemblers Silicon Compilers Experts Logic design Electronic/circuit design Device physics Artwork Applications - system design Architectures
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 18 Design Styles Full custom Standard cell Gate-array Macro-cell FPGA Combinations
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 19 Full Custom Hand drawn geometry All layers customized Digital and analog Simulation at transistor level (analog) High density High performance Long design time
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 20 Full Custom INOut Vdd Gnd
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 21 Standard cells Standard cells organized in rows (and, or, flip- flops,etc.) Cells made as full custom by vendor (not user). All layers customized Digital with possibility of special analog cells. Simulation at gate level (digital) Medium density Medium-high performance Reasonable design time
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 22 Standard cells Routing Cell IO cell
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 23 Gate-array Predefined transistors connected via metal Two types: Channel based Channel less (sea of gates) Only metallization layers customized Fixed array sizes (normally 5-10 different) Digital cells in library (and, or, flip-flops,etc.) Simulation at gate level (digital) Medium density Medium performance Reasonable design time
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 24 Gate-array Oxide isolation Gate isolation PMOS NMOS Vdd Gnd B A Out Vdd Gnd A B Out Sea of gatesChannel based NAND gate using gate isolation Can in principle be used by adjacent cell
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 25 Sea of gates Gate-array RAM
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 26 Macro cell Predefined macro blocks (Processors, RAM,etc) Macro blocks made as full custom by vendor All layers customized Digital and some analog (ADC) Simulation at behavioral or gate level (digital) High density High performance Short design time Use standard on-chip busses System on a chip DSP processor LCD cont. RAM ROMADC
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  • ENG 6090 VLSI Design Introduction to VLSI Design Lec01. 27 FPGA = Field Programmable Gate Array Programmable logic blocks Programmable connections between logic blocks No layers customized (standard devices) Digital only Low - medium performance (