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ENG 6090 – VLSI Design roduction to VLSI Design Lec01. 1 ENG6090 VLSI Design Lecture # 1

ENG 6090 – VLSI Design Introduction to VLSI Design – Lec01. 1 ENG6090 – VLSI Design Lecture # 1

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Page 1: ENG 6090 – VLSI Design Introduction to VLSI Design – Lec01. 1 ENG6090 – VLSI Design Lecture # 1

ENG 6090 – VLSI Design

Introduction to VLSI Design – Lec01. 1

ENG6090 – VLSI Design

Lecture # 1

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ENG 6090 – VLSI Design

Introduction to VLSI Design – Lec01. 2

Professor: Shawki Areibi (Off:Thorn 2335) [email protected]

Lecture Mon - Fri 10:30 - 12:00 pm Thorn2336

Laboratory ENG 2307 (Digital Design Lab)

Course Web Page www.uoguelph.ca/~sareibi

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Syllabus - VLSI Design/Reconfigurable Computing

Grading 30% Assign 10% Presentation 40% Project 20% Exams

Texts - Kang & Leblebici. “CMOS Digital Integrated Circuits”

- Rabaey. J. “Digital Integrated Circuits”, 2002

- Uyemura J. P. “Physical Design of CMOS Integrated Circuits Using L-Edit” (optional reference)

Project - Cadence Tools- Technology Files (0.18 process)

Course Expectations - Must Do a Project to Illustrate your Understanding

COURSE INFORMATION

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1. This course provides an introduction to the fundamental principles of VLSI circuit design.

2. Emphasis is placed on the design of basic building blocks of large scale digital integrated circuits and systems.

3. Understand the concept behind ASIC Design.4. Implement a complete digital system on silicon using state of

the art CAD tools.5. Understand the consequence of scaling down the dimensions

of transistors and its affect on device speed, density, ….6. Have the necessary background to complete CMOS designs

and assess which particular design style to use on a given design from FPGA to Full custom design.

ENG6090 – COURSE OBJECTIVES

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Overview of VLSI Design Cycle and MethodologiesnMOS, pMOS transistor theory and design equationsOverview of VLSI fabrication technology,Basic CMOS digital circuits, transistor-level and mask-level design,Complex logic gates, modular building blocks Data path components, ASIC design guidelines,Hardware Descriptive LanguagesReconfigurable Computing Systems (FPGAs)Physical Design Automation

ENG6090 TOPICS TO BE COVERED

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VLSI:Very Large Scale Integration

• Integration: Integrated Circuits– multiple devices on one substrate

• How large is Very Large?• SSI (small scale integration)

– 7400 series, 10-100 transistors

• MSI (medium scale)– 74000 series 100-1000

• LSI 1,000-10,000 transistors

• VLSI > 10,000 transistors

• ULSI/SLSI (some disagreement)

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Integration Improves the Design• Lower parasitics, higher clocking speed• Lower power• Physically small

Integration Reduces Manufacturing Costs• (almost) no manual assembly• About $1-5billion/fab• Typical Fab 1 city block, a few hundred people• Packaging is largest cost• Testing is second largest cost• For low volume ICs, Design Cost may swamp all manufacturing cost

WHY VLSI?

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• Specifications • IO, Goals and Objectives, Function, Costs

• Architectural Description• VLHD, Verilog, Behavioral, Large Blocks

• Logic Design

• Gates plus Registers

• Circuit Design• Transistors sized for power and speed• Discrete Logic, Technology Mapping

• Layout• Size, Interconnect, Parasitics

Levels of Design

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n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

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What is “CMOS VLSI”?

• MOS = Metal Oxide Semiconductor (This used to mean a Metal gate over Oxide insulation)

• Now we use polycrystalline silicon which is deposited on the surface of the chip as a gate. We call this “poly” or just “red stuff” to distinguish it from the body of the chip, the substrate, which is a single crystal of silicon.

• We do use metal (aluminum) for interconnection wires on the surface of the chip.

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S DG

Poly crossed over Diffusion Field effect transistor (FET)

Insulated Gate Metal Oxide Semiconductor FET

Source and Drain are Interchangeable

D

S

G

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N-Channel Enhancement mode MOS FET

• Four Terminal Device - substrate bias

–The “self aligned gate” - key to CMOS

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CMOS:Complementary MOS

• Means we are using both N-channel and P-channel type enhancement mode Field Effect Transistors (FETs).

• Field Effect- NO current from the controlling electrode into the output

– FET is a voltage controlled current device

– BJT is a current controlled current device

• N/P Channel - doping of the substrate for increased carriers (electrons or holes)

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Complementary Metal Oxide Semiconductor

PMOS

NMOS

VSS

VDD

X X’

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Four Views

Logic Transistor Layout Physical

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VLSI Design

• The real issue inVLSI is about designing systems on chips.

• The designs are complex, and we need to use structured design techniques and sophisticated design tools to manage the complexity of the design.

• We also accept the fact that any technology we learn the details of will be out of date soon.

• We are trying to develop and use techniques that will transcend the technology, but still respect it.

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Help from Computer Aided Design tools

• Tools– Editors

– Simulators

– Libraries

– Module Synthesis

– Place/Route

– Chip Assemblers

– Silicon Compilers

• Experts– Logic design

– Electronic/circuit design

– Device physics

– Artwork

– Applications - system design

– Architectures

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Design Styles

• Full custom• Standard cell• Gate-array• Macro-cell• “FPGA”• Combinations

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Full Custom

• Hand drawn geometry

• All layers customized

• Digital and analog

• Simulation at transistor level (analog)

• High density

• High performance

• Long design time

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Full Custom

IN Out

Vdd

Gnd

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Standard cells

• Standard cells organized in rows (and, or, flip-flops,etc.)

• Cells made as full custom by vendor (not user).• All layers customized• Digital with possibility of special analog cells.• Simulation at gate level (digital)• Medium density• Medium-high performance• Reasonable design time

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Standard cells

Routing

Cell

IO cell

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Gate-array

• Predefined transistors connected via metal• Two types: Channel based

Channel less (sea of gates) • Only metallization layers customized• Fixed array sizes (normally 5-10 different)• Digital cells in library (and, or, flip-flops,etc.)• Simulation at gate level (digital)• Medium density• Medium performance• Reasonable design time

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Gate-array

Oxide isolation

Gate isolation

PMOS

NMOS

Vdd

Gnd

BA

Out

Vdd

Gnd

A

B

Out

Sea of gates Channel based

NAND gate using gate isolation

Can in principle be used by adjacent cell

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Sea of gates

Gate-array

RAM

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Macro cell

• Predefined macro blocks (Processors, RAM,etc)

• Macro blocks made as full custom by vendor

• All layers customized

• Digital and some analog (ADC)

• Simulation at behavioral or gate level (digital)

• High density

• High performance

• Short design time

• Use standard on-chip busses

• “System on a chip”

DSP processor

LCDcont.

RAM

ROMADC

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FPGA = Field Programmable Gate Array

• Programmable logic blocks• Programmable connections between logic blocks • No layers customized (standard devices)• Digital only• Low - medium performance (<50 - 100MHz)• Low - medium density (up to ~100k gates)• Programmable by: SRAM, EEROM, Anti_fuse, etc• Cheap design tools on PC’s• Low development cost• High device cost

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FPGA

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Comparison

FPGA Gate array Standard cell Full custom Macro cellDensity Low Medium Medium High HighFlexibility Low (high) Low Medium High MediumAnalog No No No Yes YesPerformance Low Medium High Very high Very highDesign time Low Medium Medium High MediumDesign costs Low Medium Medium High HighTools Simple Complex Complex Very complex ComplexVolume Low Medium High High High

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High performance devices

• Mixture of full custom, standard cells and macro’s• Full custom for special blocks: Adder (data path),

etc.• Macro’s for standard blocks: RAM, ROM, etc.• Standard cells for non critical digital blocks

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Dual port RAM

Full custom

Standard cell

ASIC with mixture of full custom,RAM and standard cells

FIFO

Single port RAM

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Pentium

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ALPHA & MOTOROLA POWER PCAlpha

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New combinations

• FPGA’s with RAM, PCI interface, Processor, ADC, etc.

• Gate arrays with RAM, Processor, ADC, etc

Processor

RAM

FPGA or Gate-array logic