Design and Implementation of VLSI Systems(EN1600)

Lecture 23: Sequential Circuit Design (2/2)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

Sequencing methods

S. Reda EN160 SP’07

Sequencing timing terminology

tpdLogic Prop. Delay tpdq

Latch D-Q Prop Delay

tcdLogic Cont. Delay tpcq

Latch D-Q Cont. Delay

tpcqLatch/Flop Clk-Q Prop Delay tsetup

Latch/Flop Setup Time

tccqLatch/Flop Clk-Q Cont. Delay thold

Latch/Flop Hold Time

1. Max-Delay (setup) constraint: Flip-flops

2. Max-Delay (setup) constraint: 2-phase latches

2. Min-delay (hold) constraint: Flip-flip

S. Reda EN160 SP’07

2. Min-delay (hold) constraint: 2-phase latches

S. Reda EN160 SP’07

3. Time borrowing

Latc

h

Latc

h

Latc

h

Combinational LogicCombinational

Logic

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

(a)

(b)

Latc

h

Latc

hCombinational Logic Combinational

Logic

Loops may borrow time internally but must complete within the cycle

1

2

1 1

1

2

2

S. Reda EN160 SP’07

How much time can be borrowed?

Q1

L1

1

2

L2

1 2

Combinational Logic 1Q2D1 D2

D2

Tc

Tc/2 Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

Tborrow <= Tc/2 –(tsetup + tnonoverlap)

S. Reda EN160 SP’07

4. Clock Skew

• We have assumed zero clock skew• Clocks really have uncertainty in arrival time

– Decreases maximum propagation delay– Increases minimum contamination delay– Decreases time borrowing

S. Reda EN160 SP’07

4. Skew: flip-flops

S. Reda EN160 SP’07

4. Skew: 2-phase latches