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Lecture 11: Sequential Circuit › harris › class › e158 › lect11-seq.pdf 11: Sequential Circuits CMOS VLSI DesignCMOS VLSI Design 4th Ed. 4Sequencing Cont. qIf tokens moved

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  • Lecture 11: Sequential Circuit Design

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 2

    Outline q Sequencing q Sequencing Element Design q Max and Min-Delay q Clock Skew q Time Borrowing q Two-Phase Clocking

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 3

    Sequencing q Combinational logic

    – output depends on current inputs q Sequential logic

    – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline

    CL

    clk

    in out

    clk clk clk

    CL CL

    PipelineFinite State Machine

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 4

    Sequencing Cont. q If tokens moved through pipeline at constant speed,

    no sequencing elements would be necessary q Ex: fiber-optic cable

    – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses

    q This is called wave pipelining in circuits q In most circuits, dispersion is high

    – Delay fast tokens so they don t catch slow ones.

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 5

    Sequencing Overhead q Use flip-flops to delay fast tokens so they move

    through exactly one stage each cycle. q Inevitably adds some delay to the slow tokens q Makes circuit slower than just the logic delay

    – Called sequencing overhead q Some people call this clocking overhead

    – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 6

    Sequencing Elements q Latch: Level sensitive

    – a.k.a. transparent latch, D latch q Flip-flop: edge triggered

    – A.k.a. master-slave flip-flop, D flip-flop, D register q Timing Diagrams

    – Transparent – Opaque – Edge-trigger

    D Fl op

    La tc

    h

    Q

    clk clk

    D Q

    clk

    D

    Q (latch)

    Q (flop)

    D Fl op

    La tc

    h

    Q

    clk clk

    D Q

    clk

    D

    Q (latch)

    Q (flop)

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 7

    Latch Design q Pass Transistor Latch q Pros

    + Tiny + Low clock load

    q Cons – Vt drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input

    D Q

    f

    Used in 1970 s

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 8

    Latch Design q Transmission gate

    + No Vt drop - Requires inverted clock D Q

    f

    f

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 9

    Latch Design q Inverting buffer

    + Restoring + No backdriving + Fixes either

    • Output noise sensitivity • Or diffusion input

    – Inverted output

    D

    f

    f

    X Q

    D Q

    f

    f

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 10

    Latch Design q Tristate feedback

    + Static – Backdriving risk

    q Static latches are now essential because of leakage

    f

    f f

    f

    QD X

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 11

    Latch Design q Buffered input

    + Fixes diffusion input + Noninverting

    f

    f

    QD X

    f

    f

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 12

    Latch Design q Buffered output

    + No backdriving

    q Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading

    f

    f

    Q

    D X

    f

    f

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 13

    Latch Design q Datapath latch

    + smaller + faster - unbuffered input

    f

    f f

    f

    Q

    D X

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 14

    Flip-Flop Design q Flip-flop is built as pair of back-to-back latches

    D Q

    f

    f

    f

    f

    X

    D

    f

    f

    f

    f

    X

    Q

    Q f

    f

    f

    f

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 15

    Enable q Enable: ignore clock when en = 0

    – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew

    D Q

    La tc

    h

    D Q

    en

    en

    f

    f

    La tc

    hD Q

    f

    0

    1

    en

    La tc

    h

    D Q

    f en

    D Q

    f

    0

    1

    en D Q

    f en

    Fl op

    Fl op

    Fl op

    Symbol Multiplexer Design Clock Gating Design

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 16

    Reset q Force output low when reset asserted q Synchronous vs. asynchronous

    D

    f

    f

    f

    f

    Q

    Q f

    f

    f

    f

    reset

    D

    f

    f f

    f

    f

    f

    Qf

    f

    D reset

    f

    f

    Q f

    f

    D reset

    reset

    f

    f

    reset

    Synchronous R eset

    Asynchronous R eset

    Sym bol F

    lo p

    D Q La

    tc h

    D Q

    reset reset

    f f

    f

    f

    Q

    reset

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 17

    Set / Reset q Set forces output high when enabled

    q Flip-flop with asynchronous set and reset

    D

    f

    f

    f

    f f

    f

    Q

    f

    f

    reset

    set reset

    set

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 18

    Sequencing Methods q Flip-flops q 2-Phase Latches q Pulsed Latches

    Flip-Flops Fl

    op La

    tc h

    Fl op

    clk

    f1

    f2

    fp

    clk clk

    La tc

    h

    La tc

    h

    fp fp

    f1 f1f2

    2-Phase Transparent Latches Pulsed Latches

    Combinational Logic

    Combinational Logic

    Combinational Logic

    Combinational Logic

    La tc

    h

    La tc

    h

    Tc

    Tc/2 tnonoverlap tnonoverlap

    tpw

    Half-Cycle 1 Half-Cycle 1

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 19

    Timing Diagrams

    Fl op

    A

    Y

    tpd Combinational

    LogicA Y

    D Q

    clk clk

    D

    Q

    La tc h

    D Q

    clk clk

    D

    Q

    tcd

    tsetup thold

    tccq

    tpcq

    tccq

    tsetup thold tpcq

    tpdq tcdq

    tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk->Q Prop. Delay tccq Latch/Flop Clk->Q Cont. Delay tpdq Latch D->Q Prop. Delay tcdq Latch D->Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time

    Contamination and Propagation Delays

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 20

    Max-Delay: Flip-Flops

    F1 F2

    clk

    clk clk

    Combinational Logic

    Tc

    Q1 D2

    Q1

    D2

    tpd

    tsetup tpcq

    tpd ≤ Tc − tsetup + tpcq( ) sequencing overhead ! "# $#

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 21

    Max Delay: 2-Phase Latches

    Tc

    Q1

    L1

    f1

    f2

    L2 L3

    f1 f1f2

    Combinational Logic 1

    Combinational Logic 2

    Q2 Q3D1 D2 D3

    Q1

    D2

    Q2

    D3

    D1

    tpd1

    tpdq1

    tpd2

    tpdq2

    tpd = tpd1 + tpd 2 ≤ Tc − 2tpdq( ) sequencing overhead !"#

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 22

    Max Delay: Pulsed Latches

    Tc

    Q1 Q2D1 D2

    Q1

    D2

    D1

    fp

    fp fp

    Combinational LogicL1 L2

    tpw

    (a) tpw > tsetup

    Q1

    D2 (b) tpw < tsetup

    Tc

    tpd

    tpdq

    tpcq tpd tsetup

    tpd ≤ Tc − max tpdq ,tpcq + tsetup − tpw( ) sequencing overhead

    ! "#### $####

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 23

    Min-Delay: Flip-Flops

    holdcd ccqt t t³ - CL

    clk

    Q1

    D2

    F1

    clk

    Q1

    F2

    clk

    D2

    tcd

    thold

    tccq

  • CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 24

    Min-Delay: 2-Phase Latches

    tcd1,tcd 2 ≥ thold − tccq − tnonoverlap CL

    Q1

    D2

    D2

    Q1

    f1

    L1

    f2

    L2

    f1

    f2

    tnonoverlap

    tcd

    thold

    tccq

    Hold time reduced by nonoverlap

    Paradox: hold applies twice each cycle, vs. only once for flops.

    But a flop is made of two latches!

  • CMOS VLSI Design

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