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Lecture 18: Datapath Functional Units

# Lecture 18: Datapath Functional Unitsuser.engineering.uiowa.edu/~vlsi1/notes/lect18.pdf · 18: Datapath Functional Units 19CMOS VLSI DesignCMOS VLSI Design 4th Ed. CSA Application

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### Text of Lecture 18: Datapath Functional Unitsuser.engineering.uiowa.edu/~vlsi1/notes/lect18.pdf · 18:...

Lecture 18: DatapathFunctionalUnits

18: Datapath Functional Units 2CMOS VLSI DesignCMOS VLSI Design 4th Ed.

18: Datapath Functional Units 3CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Comparators0’s detector: A = 00…0001’s detector: A = 11…111Equality comparator: A = BMagnitude comparator: A < B

18: Datapath Functional Units 4CMOS VLSI DesignCMOS VLSI Design 4th Ed.

1’s & 0’s Detectors1’s detector: N-input AND gate0’s detector: NOTs + 1’s detector (N-input NOR)

A0

A1

A2

A3

A4

A5

A6

A7

allones

A0

A1

A2

A3

allzeros

allones

A1

A2

A3

A4

A5

A6

A7

A0

18: Datapath Functional Units 5CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Equality ComparatorCheck if each bit is equal (XNOR, aka equality gate)1’s detect on bitwise equality

A[0]B[0]

A = B

A[1]B[1]

A[2]B[2]

A[3]B[3]

18: Datapath Functional Units 6CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Magnitude ComparatorCompute B – A and look at signB – A = B + ~A + 1For unsigned numbers, carry out is sign bit

A0

B0

A1

B1

A2

B2

A3

B3

A = BZ

C

A B≤

N A B≥

18: Datapath Functional Units 7CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Signed vs. UnsignedFor signed numbers, comparison is harder– C: carry out– Z: zero (all bits of A – B are 0)– N: negative (MSB of result)– V: overflow (inputs had different signs, output sign ≠ B)– S: N xor V (sign of result)

18: Datapath Functional Units 8CMOS VLSI DesignCMOS VLSI Design 4th Ed.

ShiftersLogical Shift:– Shifts number left or right and fills with 0’s

• 1011 LSR 1 = 0101 1011 LSL1 = 0110Arithmetic Shift:– Shifts number left or right. Rt shift sign extends

• 1011 ASR1 = 1101 1011 ASL1 = 0110Rotate:– Shifts number left or right and fills with lost bits

• 1011 ROR1 = 1101 1011 ROL1 = 0111

18: Datapath Functional Units 9CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Funnel ShifterA funnel shifter can do all six types of shiftsSelects N-bit field Y from 2N–1-bit input– Shift by k bits (0 ≤ k < N)– Logically involves N N:1 multiplexers

18: Datapath Functional Units 10CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Funnel Source Generator

Rotate RightLogical RightArithmetic Right

Rotate LeftLogical/Arithmetic Left

18: Datapath Functional Units 11CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Array Funnel ShifterN N-input multiplexers– Use 1-of-N hot select signals for shift amount– nMOS pass transistor design (Vt drops!)

k[1:0]

s0s1s2s3Y3

Y2

Y1

Y0

Z0Z1Z2Z3Z4

Z5

Z6

left Inverters & Decoder

18: Datapath Functional Units 12CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Logarithmic Funnel ShifterLog N stages of 2-input muxes– No select decoding needed

18: Datapath Functional Units 13CMOS VLSI DesignCMOS VLSI Design 4th Ed.

32-bit Logarithmic FunnelWider multiplexers reduce delay and powerOperands > 32 bits introduce datapath irregularity

18: Datapath Functional Units 14CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Barrel ShifterBarrel shifters perform right rotations using wrap-around wires.Left rotations are right rotations by N – k = k + 1 bits.Shifts are rotations with the end bits masked off.

18: Datapath Functional Units 15CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Logarithmic Barrel Shifter

Right shift only

Right/Left shift Right/Left Shift & Rotate

18: Datapath Functional Units 16CMOS VLSI DesignCMOS VLSI Design 4th Ed.

32-bit Logarithmic BarrelDatapath never wider than 32 bitsFirst stage preshifts by 1 to handle left shifts

18: Datapath Functional Units 17CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Multi-input AddersSuppose we want to add k N-bit words– Ex: 0001 + 0111 + 1101 + 0010 = 10111

Straightforward solution: k-1 N-input CPAs– Large and slow

+

+

0001 0111

+

1101 0010

10101

10111

1000

18: Datapath Functional Units 18CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Carry Save AdditionA full adder sums 3 inputs and produces 2 outputs– Carry output has twice weight of sum output

N full adders in parallel are called carry save adder– Produce N sums and N carry outs

Z4Y4X4

S4C4

Z3Y3X3

S3C3

Z2Y2X2

S2C2

Z1Y1X1

S1C1

XN...1 YN...1 ZN...1

SN...1CN...1

n-bit CSA

18: Datapath Functional Units 19CMOS VLSI DesignCMOS VLSI Design 4th Ed.

CSA ApplicationUse k-2 stages of CSAs– Keep result in carry-save redundant form

Final CPA computes actual result

4-bit CSA

5-bit CSA

0001 0111 1101 0010

+

10110101_

01010_ 00011

0001 0111+1101 10110101_

XYZSC

0101_ 1011 +0010 0001101010_

XYZSC

01010_+ 00011 10111

ABS

10111

18: Datapath Functional Units 20CMOS VLSI DesignCMOS VLSI Design 4th Ed.

MultiplicationExample:

M x N-bit multiplication– Produce N M-bit partial products– Sum these to produce M+N-bit product

1100 : 1210 0101 : 510 1100 0000 1100 000000111100 : 6010

multipliermultiplicand

partialproducts

product

18: Datapath Functional Units 21CMOS VLSI DesignCMOS VLSI Design 4th Ed.

General FormMultiplicand: Y = (yM-1, yM-2, …, y1, y0)Multiplier: X = (xN-1, xN-2, …, x1, x0)

Product:1 1 1 1

0 0 0 0

2 2 2M N N M

j i i jj i i j

j i i j

P y x x y− − − −

+

= = = =

⎛ ⎞ ⎛ ⎞= =⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠

∑ ∑ ∑∑

x0y5 x0y4 x0y3 x0y2 x0y1 x0y0

y5 y4 y3 y2 y1 y0

x5 x4 x3 x2 x1 x0

x1y5 x1y4 x1y3 x1y2 x1y1 x1y0

x2y5 x2y4 x2y3 x2y2 x2y1 x2y0

x3y5 x3y4 x3y3 x3y2 x3y1 x3y0

x4y5 x4y4 x4y3 x4y2 x4y1 x4y0

x5y5 x5y4 x5y3 x5y2 x5y1 x5y0

p0p1p2p3p4p5p6p7p8p9p10p11

multipliermultiplicand

partialproducts

product

18: Datapath Functional Units 22CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Dot DiagramEach dot represents a bit

partial products

multiplier x

x0

x15

18: Datapath Functional Units 23CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Array Multipliery0y1y2y3

x0

x1

x2

x3

p0p1p2p3p4p5p6p7

B

ASin Cin

SoutCout

BA

CinCout

Sout

Sin

=

CSAArray

CPA

critical path BA

Sout

Cout CinCout

Sout

=Cin

BA

18: Datapath Functional Units 24CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Rectangular ArraySquash array to fit rectangular floorplan

y0y1y2y3

x0

x1

x2

x3

p0

p1

p2

p3

p4p5p6p7

18: Datapath Functional Units 25CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Fewer Partial ProductsArray multiplier requires N partial productsIf we looked at groups of r bits, we could form N/r partial products.– Faster and smaller?– Called radix-2r encoding

Ex: r = 2: look at pairs of bits– Form partial products of 0, Y, 2Y, 3Y– First three are easy, but 3Y requires adder

18: Datapath Functional Units 26CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Booth EncodingInstead of 3Y, try –Y, then increment next partial product to add 4YSimilarly, for 2Y, try –2Y + 4Y in next partial product

18: Datapath Functional Units 27CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Booth HardwareBooth encoder generates control lines for each PP– Booth selectors choose PP bits

18: Datapath Functional Units 28CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Sign ExtensionPartial products can be negative– Require sign extension, which is cumbersome– High fanout on most significant bit

multiplier x

x0

x15

0

00

x-1

x16x17

ssssssssssssssss

ssssssssssssss

ssssssssssss

ssssssssss

ssssssss

ssssss

ssss

ss

PP0

PP1

PP2

PP3

PP4

PP5

PP6

PP7

PP8

18: Datapath Functional Units 29CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Simplified Sign Ext.Sign bits are either all 0’s or all 1’s– Note that all 0’s is all 1’s + 1 in proper column– Use this to reduce loading on MSB

s111111111111111s

s1111111111111s

s11111111111s

s111111111s

s1111111s

s11111s

s111s

s1s

PP0

PP1

PP2

PP3

PP4

PP5

PP6

PP7

PP8

18: Datapath Functional Units 30CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Even Simpler Sign Ext.No need to add all the 1’s in hardware– Precompute the answer!

ssss

ss1

ss1

ss1

ss1

ss1

ss1

ss

PP0PP1PP2PP3PP4PP5PP6PP7PP8

18: Datapath Functional Units 31CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Advanced MultiplicationSigned vs. unsigned inputsHigher radix Booth encodingArray vs. tree CSA networks

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