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Running Verilog-HDL file – tutorial using Vivado 2017.3 LSI Design Contest 2018 2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 1

Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

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Page 1: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

Running Verilog-HDL

file – tutorial

using Vivado 2017.3

LSI Design Contest 2018

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 1

Page 2: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

Open Vivado

Note that the version used here is 2017.3

Next, click the 「Create Project…」 as shown

in the figure.

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 2

Opening Vivado

Page 3: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 3

Locating project file

Create a New Vivado project will come out, clik next.

Assign the location to your selected folder

Enter the name

For example : NN_test

Click, next

Project type terminal will come out

click next

Add Sources terminal will come out

click next

Add Constraints terminal will come out

click next

Default part terminal will come out

select your specified boards

and finish.

Page 4: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 4

Specifying board

Default part terminal will come out

select your specified boards

click next

Click finish.

Page 5: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 5

Locating project file

A new folder will be created in your selected location

contents

Page 6: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

Download the zip file from LSI design contest HP.

Link : http://www.lsi-contest.com/shiyou_4e.html

(Verilog file for simulation)

Extract the file

There will be around 45 Verilog file

Move all the Verilog file into NN_test folder

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 6

Download Verilog file

http://www.lsi-contest.com/shiyou_4e.html
Page 7: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 7

Add source file

Click Add source

① Click this button

② Click Next>

Page 8: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 8

Add source file

Click Add files

① Click this button

② Click OK,

then Finish

Page 9: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 9

Synthesize the project

In Flow Navigator, select

SYNTHESIS

Click Run Synthesis

After synthesis completed, run

implementation

① Click run synthesize

② Click OK

③ Click Cancel

Page 10: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 10

Generate Bitstream

In Flow Navigator, select

PROGRAM AND DEBUG

Click Generate Bitstream

When you program device,

you should turn on board.

① Click run Generate Bitstream

② Click OK

③ Click Cancel

④ Click Auto Connect

⑤ Click Program device

Page 11: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 11

Simulate the project

Select Simulation

Click Run Simulation

Click Run Behavioral Simulation

① Select

Simulation

② Click Run Simulation,

then Run Behavioral

Simulation

Page 12: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

Vivado simulator will open

Choose forward block in Scope

Choose signal b2_1 until w3_32

Drag the signal into simulator

Choose forward > selector block in instance and process name

Choose signal enable update

Drag the signal into simulator

See the figure in the next slide…

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 12

Vivado Simulator

Page 13: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 13

Vivado Simulator

① open forward block

② drag this signal into simulator

Page 14: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 14

Vivado Simulator

Click the restart button

① click restart button

Page 15: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 15

Vivado Simulator

Click the Run All button① click Run All button

Page 16: Running Verilog-HDL file tutorial using Vivado 2017 Verilog-HDL file...Vivado simulator will open Choose forward block in Scope Choose signal b2_1 until w3_32 Drag the signal into

New weight and bias will be updated every time the enable update signal is

active.

2017/11/10 Copyrights 2017-2018 LSI Design Contest. All Rights Reserved. 16

Conclusion


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