ADVANCED VLSI CHAP4-5

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    Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf

    Topics

    Switch networks.

    Combinational testing.

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    Boolean functions and switches

    pseudo-AND

    pseudo-OR

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    Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf

    Driving switch outputs

    If switch network output is not connected to

    power supply through switch path, output

    will float.

    Switch network inputs may be connected to

    power supply or logic signals.

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    Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf

    Switching logic signals

    b

    a

    b

    a

    ab + ab

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    Switch multiplexer

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    Charge sharing

    Interior nodes in a switch network may not

    be driven.

    Charge can accumulate on small parasitic

    capacitances.

    Shared charge can produce erroneous output

    values.

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    Charge division

    At undriven nodes, charge is divided

    according to capacitance ratio.

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    Charge sharing example

    Long chains of switches have intermediate

    nodes which may be disconnected from

    power supplies.

    CabCia Cbc

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    Charge over time

    time i Cia a Cib b Cbc c C

    0 1 1 1 1 1 1 1 11 0 0 1 0 0 1 0 1

    2 0 0 0 1/2 1 1/2 0 1

    3 0 0 0 1/2 0 3/4 1 3/4

    4 0 0 0 0 0 3/4 0 3/4

    5 0 0 0 3/8 1 3/8 0 3/4

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    Avoiding charge sharing

    Make sure that for every input combination

    there is a path from the power supply to the

    output.

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    Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf

    Manufacturing testing

    Errors are introduced during manufacturing.

    Testing verifies that chip corresponds to

    design.

    Varieties of testing:

    functional testing;

    performance testing (binning chips by speed).

    Testing also weeds out infant mortality.

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    Testing and faults

    Fault model:

    possible locations of faults;

    I/O behavior produced by the fault.

    Good news: if we have a fault model, we

    can test the network for every possible

    instantiation of that type of fault.

    Bad news: it is difficult to enumerate all

    types of manufacturing faults.

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    Stuck-at-0/1 faults

    Stuck-at-0/1: logic gate output is always

    stuck at 0 or 1, independent of input values.

    Correspondence to manufacturing defects

    depends on logic family.

    Experiments show that 100% stuck-at-0/1

    fault coverage corresponds to high overallfault coverage.

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    Testing procedure

    Testing procedure:

    set gate inputs;

    observe gate output;

    compare fault-free and observed gate output.

    Test vector: set of gate inputs applied to a

    system.

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    Stuck-at faults in gates

    a b OK SA0 SA1

    0 0 1 0 1

    0 1 1 0 1

    1 0 1 0 1

    1 1 0 0 1

    a b OK SA0 SA1

    0 0 1 0 1

    0 1 0 0 1

    1 0 0 0 1

    1 1 0 0 1

    NAND NOR

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    Testing single gates

    Three ways to test NAND for stuck-at-0,

    only one way to test it for stuck-at-1.

    Three ways to test NOR for stuck-at-1, onlyone way to test it for stuck-at-0.

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    Testing combinational networks

    100% coverage: test every gate for

    stuck-at-0;

    stuck-at-1.

    Assume that there is only one faulty gate

    per network.

    Most networks require more than one testvector to test all gates.

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    Multiple test example

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    Example

    Can test both NANDs for stuck-at-0

    simultaneously (abc = 000).

    Cannot test both NANDs for stuck-at-1simultaneously due to inverter. Must use

    two vectors.

    Must also test inverter.

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    Stuck-at-open/closed model

    Models transistors always on/off.

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    Stuck-open behavior

    If t1 is stuck open (switch cannot be closed),

    there can be no path from VDD to output

    capacitance. Testing requires two cycles:

    must discharge capacitor;

    try to operate t1 to see if capacitor can becharged.

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    Delay fault

    Delay falls outside acceptable limits:

    gate delay fault assumes that all delays are

    lumped into one gate;path delay fault models delay problems along

    path through network.

    Delay problems reduce yield:performance problems;

    functional problems in some types of circuits.

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    Combinational network testing

    Two parts to testing:

    controlling the inputs of (possibly interior)

    gates;observing the outputs of (possibly interior)

    gates.

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    Combinational testing example

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    Testing procedure

    Goal: test gate D for stuck-at-0 fault.

    First step: justify 0 values on gate inputs.

    Work backward from gate to primary

    inputs:

    w1 = 0 (A output = 0);

    i1 = i2 = 1.

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    Testing procedure, contd

    Observe the fault at a primary output:

    o1 gives different values if D is true/faulty.

    Work forward and backward:

    Fs other input must be 0 to detect true/fault.

    Justify 0 at Es output.

    In general, may have to propagate fault

    through multiple levels of logic to primary

    outputs.

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    Fault masking

    Redundant logic can mask faults:

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    Redundancy example

    Testing NOR for SA0 requires setting both

    inputs to 0.

    Network topology ensures that one NORinput will always be 1.

    Function reduces to 0:

    f = (ab) + b = a + b + b = 0.

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    Redundancies and testing

    Redundant logic cannot be controlled.

    Observations requiring control of redundant

    logic may not be possible.

    Redundant logic should be minimized to

    eliminate redundancy. Redundancies can

    introduce delay faults and other problems.