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7/28/2019 ADVANCED VLSI CHAP6-2
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Topics
Multipliers.
7/28/2019 ADVANCED VLSI CHAP6-2
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Elementary school algorithm
0 1 1 0 multiplicand
x 1 0 0 1 multiplier
0 1 1 0
+ 0 0 0 0
0 0 1 1 0
+ 0 0 0 00 0 0 1 1 0
+ 0 1 1 0
0 1 1 0 1 1 0
partial product
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Word serial multiplier
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Combinational multiplier
Uses n adders, eliminates registers:
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Array multiplier
Array multiplier is an efficient layout of a
combinational multiplier.
Array multipliers may be pipelined to
decrease clock period at the expense of
latency.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Array multiplier organization
0 1 1 0
x 1 0 0 1
0 1 1 0
+ 0 0 0 0
0 0 1 1 0
+ 0 0 0 00 0 0 1 1 0
+ 0 1 1 0
0 1 1 0 1 1 0
product
skew array
for rectangularlayout
multiplicand
multiplier
7/28/2019 ADVANCED VLSI CHAP6-2
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Unsigned array multiplier
+
x0y0x1y0x2y0
xny0
0
x0y1+ x1y1
0
+ x0y2+ x1y2
+ 0+
P(2n-1) P(2n-2) P0
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Baugh-Wooley multiplier
Algorithm for twos-complement
multiplication.
Adjusts partial products to maximize
regularity of multiplication array.
Moves partial products with negative signs
to the last steps; also adds negation ofpartial products rather than subtracts.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Booth multiplier
Encoding scheme to reduce number of
stages in multiplication.
Performs two bits of multiplication at
oncerequires half the stages.
Each stage is slightly more complex than
simple multiplier, but adder/subtracter isalmost as small/fast as adder.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Booth encoding
Twos-complement form of multiplier:
y = -2nyn + 2n-1yn-2 + 2
n-2yn-2 + ...
Rewrite using 2a = 2a+1 - 2a:
y = -2n(yn-1-yn) + 2n-1(yn-2 -yn-1) + 2
n-2(yn-3 -yn-2)
+ ...
Consider first two terms: by looking at threebits of y, we can determine whether to add
x, 2x to partial product.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Booth actions
yi yi-1 yi-2 increment
0 0 0 0
0 0 1 x0 1 0 x
0 1 1 2x
1 0 0 -2x
1 0 1 -x
1 1 0 -x
1 1 1 0
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Booth example
x = 011001 (2510), y = 101110 (-1810).
y1y0y-1 = 100, P1 = P0 - (10 011001) =
11111001110.
y3y2y1= 111, P2 = P1 0 = 11111001110.
y5y4y3= 101, P3 = P2 - 0110010000 =
11000111110.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Booth structure
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Wallace tree
Reduces depth of adder chain.
Built from carry-save adders:
three inputs a, b, c
produces two outputs y, z such that y + z = a +
b + c
Carry-save equations:yi = parity(ai,bi,ci)
zi = majority(ai,bi,ci)
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Wallace tree structure
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Wallace tree operation
At each stage, i numbers are combined to
form ceil(2i/3) sums.
Final adder completes the summation.
Wiring is more complex.
Can build a Booth-encoded Wallace tree
multiplier.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Serial-parallel multiplier
Used in serial-arithmetic operations.
Multiplicand can be held in place by
register.
Multiplier is shfited into array.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Serial-parallel multiplier
structure