ADVANCED VLSI CHAP8-5

7/28/2019 ADVANCED VLSI CHAP8-5

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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf

Topics

Testability and architecture. Design methodologies. Multiprocessor system-on-chip.


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Architecture testing

Want to make system as testable as possible with minimum cost in hardware,testing time.

Can use knowledge of architecture to helpchoose testability points.

May want to modify architecture toimprove testability.


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Some scan latches are moreuseful than others

Acyclic register-transfer graphs are easy totest.

Register-transfers with feedback are harder to test state becomes contaminatedduring test.

When choosing partial scan registers,choose feedback paths first.


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Identifying partial scanopportunities

Construct register graph, which showsconnections between registers:

nodes are registers; edge between two nodes if there is a

combinational path between them.

Sequential depth is distance from primaryinput to a node.


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Analyzing register graphs

High sequential depth implies that theregister is harder to test.

Registers contained register-graph cycles(FF2-FF3) are hard to test (although self-loops are not hard).

Add partial scan registers to effectivelyreduce sequential depth of node and itsneighbors.


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Built-in self test (BIST)

Includes on-chip machine responsible for: generating tests;

evaluating correctness of tests. Allows many tests to be applied. Cant afford large memory for test

results rely on compression andstatistical analysis.


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Generating vectors

Use a linear-feedback shift register to generatea pseudo-random sequence of bit vectors:


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BIST architecutre

One LFSR to generates test sequence. Another LFSR captures/compresses

results. Can store a small number of signatures

which contain expected compressed resultfor valid system.


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Design methodologies

Every company has its own designmethodology.

Methodology depends on: size of chip; design time constraints;

cost/performance; available tools.


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Generic design flow

architecturalsimulation

floorplan

register-transfer design

logicdesign

circuitdesignlayout

functional/ performance

verification

testability

detailed

specs

tapeout


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Specification and planning

Driven by contradictory impulses: customer-centric concerns about cost,

performance, etc.; forecasts of feasibility of cost and performance.

Features, performance, power, etc. may be

negotiated at early stages; negotiation atlater stages creates problems.


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Estimation and planning

Estimation techniques vary with module: memories may be generated once size is

known; data paths may be estimated from previous

design;

controllers are hard to estimate without details. Estimates must include speed, area, power.


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Floorplanning and budgeting

The purpose of early floorplanning is toestablish budgets for each major

component: area, delay, power, etc. The project leader must ensure that

budgets are met at all times. If it becomes

clear that meeting a budget for acomponent is impossible, the floorplanmust be redone ASAP.


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Logic design

For controllers, good state assignment isusually requires CAD tools.

Logic synthesis is an option: very good for non-critical logic; can work well for speed-critical logic.

Logic synthesis system may be sensitive tochanges in the input specification.


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Circuit/layout design

Tasks: size transistors;

draw layout. Alternative design styles:

full custom logic (very tedious);

standard cell. Full custom most likely for datapaths, least

likely for random logic off critical path.


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Design validation

Must verify: layout (design rule check = DRC);

circuit performance; clock distribution; functionality;

power consumption / power bussing.


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Testing

Automatic test pattern generation = ATPG. Must verify that circuit can be tested,

generate a compact set of manufacturingtest vectors.

Test vectors often comprised of vectorstaken from simulation + ATPG-generatedvectors.


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Tapeout

Tapeout: generating final files for masks.Shipped to mask-making house.

Pre-tapeout verification is importancesince it will take months to get results fromfab.

Tapeout party follows. Size of partydepends on importance of chip design

project.


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Multiprocessor systems-on-chips

System-on-chip is a complete integratedsystem.

MPSoC has more than one processingelement:

CPU.

DSP. Hardwired accelerator.


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Styles of MPSoC

Homogeneous, as in multicore. Heterogeneous:

Several different types of processing elements. Non-uniform memory system, with different

PEs accessing different parts of memory.

Non-uniform interconnect structure.


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MPSoCs and IP

MPSoCs require a lot of IP: Processing elements.

Memories. Networks-on-chip. I/O devices.


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Trimedia TM-1300 architecture

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ADVANCED VLSI CHAP8-5