Advanced in the VLSI Design Flow.pdf

02/26/09 1

Advances in the Nanometer VLSI Design Flow

By Venkatesh Prasad

Nanochip Offering: RV-VLSI

Established in 2006

Conceived, implemented and managed by

Nanochip under its ECS business line in

collaboration with RV group of educational

institutions

8000 sq ft talent incubation center

Located in the center of the city

Company Confidential www.nanochipsolutons.com

ECS Offerings Educational Consultancy Services (ECS)

Academics VLSI, Embedded TTP course material

oIndustry Approved

Setting up and managing finishing schools

Product Companies Domain specific advanced and on-boarding

Corporate Training Company Confidential www.nanochipsolutons.com


Educational Consulting Service

Manages RV-VLSI Design Center on behalf of RV

Group of Educational Institutions

RV-VLSI Class Rooms Experiential Learning

Shrama -I


RV-VLSI Design Center Imparting Experience

Abhyas TALENT INCUBATION CENTER


Multi CPU machines

Access through SUNRAY Linux 64 bit architecture Industry Standard EDA tool access

Access to latest processes and technology

RV-VLSI Datacenter


RV-VLSI Team

Dedicated fulltime Faculty with domain expertise B. K. Srinath

25 yrs, Ex- BEL, Ex-TI Fullcustom, PD and CAD

Dr. Preetham Lakshmikanthan Phd. 10 yrs, Ex-Intel RTL Verification, SV, FPGA

Vibhav T Gold Medalist IIT-B 25 Yrs Ex- TEL RTL Design, FPGA, System Design


RV-VLSI: Enrollment Statistics

Total No. of students enrolled till date

1512

Students from different Colleges

nationwide

> 300 Colleges

Students from no. of States

18 -- (Highest AP, Second highest is Delhi NCR

No. of Countries

6 -- (USA, UK, Germany, Dubai, Singapore, Australia)

No. of Product Companies for

Placement

Around 25 Product Companies

No. of Service Companies for

placement

More than 42 Service Companies


[email protected] www.nanochipsolutions.com Company Confidential

10

A bit of history


11

It all started in 1947


12

Picture Of First IC

Source: http://www.ti.com/corp/docs/kilbyctr/downloadphotos.shtml Jack Kilby with his notes Today a Billion Transistor are packed in one chip ever wondered how this is designed, fabricated and what challenges come along the way ?


13

Layout of an IC say a decade ago

Memories D

igita

l Blo

ck

Analog

FPS: State Of The Art Flows, Proven IP And Efficient Communications With Global Teams

I/O Ring

I/O

Rin

g A Analog D


14

Layout of an IC just a few years ago

I/O Ring

Memories Digital Block

Analog


I/O Ring


15

Layout of a Typical IC -- Today

I/O Ring

Memories Digital Block

Analog


I/O Ring

D M2

A


16

Sample Layouts

10580 x 7840

6 layer metal

11460 x 8000

8 layer metal


17

Sample Layouts

Die size is 4609.6 x 6410.6

18,757,178 devices 15,887,555 devices


18

Yesterdays Chip Todays Block -- SOC


19

Basic Design Flow

Specifications

Simulation

Arch & Circuit Design

Layout, checks & fabrication

Post Silicon Validation

Question: Have these BASIC steps changed ?


20

ASIC AMS VLSI Design Flow

Design (FE) Concept Implementation Physical Design (BE)

RTL

Verification

RTL Analysis

Synthesis & STA analysis

DFT

P&R CTS

PEX and BA

DRC &LVS

TO

MRD

Specification

Architectural Specification

Micro Architectural


21

Design Challenges

Market Pressures Designs must work at a high frequency Must consume less power Must be cheap (small die size or area and yield)

Improving one will make the other two worst do you Know why ??

www.mentor.com 2013 Mentor Graphics Corp. Company Confidential

The Power Optimization Landscape

Low Power Session - Verification Seminar 22

n System architecture level SW-HW partitioning Single core vs Multi cores Bus and memory architecture

n Micro-architecture level Frequency and voltage scaling Memory/register file banking Auto-inferencing of appropriate FIFOs

n RTL Combinational, sequential clock gating Memory, data gating Power gating

n Gate/Physical implementation Multi-Vdd, Multi-Vth technology mapping Clock network optimization

RTL Clock gating, Power gating

Physical Clock tree, multi-Vth

Mfg

System Design/Architecture Algorithms, Pipelining, Sharing, Power Domains

Opportunity to Influence Power


IEEE Std 1801-2009

UPF

Low Power Design and Verification Flow RTL can remain untouched and reused; UPF adds power intent

n RTL is augmented with UPF To define the power architecture for

a given implementation

n RTL + UPF verification Ensures that the power architecture

is complete and consistent with expected power states of the design

Ensures that the design will work correctly under power management with this power architecture

n RTL + UPF implementation Synthesis, test insertion, place &

route, etc. UPF may be updated by the user or

the tool

n NL + UPF verification Power aware equivalence checking,

static analysis, simulation, emulation, etc.

UPF

UPF

UPF

Sim

ulat

ion,

Po

wer

An

alys

is/O

pti

miz

atio

n,

Logi

cal E

quiv

alen

ce C

heck

ing,

Netlist

Synthesis

Netlist

Place & Route

RTL



------------------------------------------------------------ ----- QuestaSim Power Aware Design Element Report File ----- ------------------------------------------------------------ ------------------------------------------------------------ PD_top: {Path1} = scope /testbench/axi_dut

PD_top: {Path337} = scope /testbench/axi_dut/fpu_inst

PD_top: {Path338} = scope /testbench/axi_dut/pcu_inst PD_top: {Path339} = scope /testbench/axi_dut/pcu_inst/sys_pcu/pcu1

PD_top: {Path340} = scope /testbench/axi_dut/pcu_inst/sys_pcu/pcu2

PD_top: {Path341} = scope /testbench/axi_dut/mem_inst

PD_fpu: {Path342} = scope /testbench/axi_dut/fpu_inst/fpu_dut PD_fpu: {Path343} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_post_norm_sqrt

PD_fpu: {Path344} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_sqrt PD_fpu: {Path345} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_pre_norm_sqrt

PD_fpu: {Path346} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_post_norm_div

PD_fpu: {Path347} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_serial_div PD_fpu: {Path348} = scope /testbench/axi_dut/fpu_inst/fpu_dut/i_pre_norm_div

---------------------------------------------------------- ----- QuestaSim Power Aware Architecture Report File ----- ----------------------------------------------------------

---------------------------------------------------------- Power Domain: PD_fpu, File: /home/work/dpframe/upf/subsys.upf(10).

Creation Scope: /testbench/axi_dut Primary Supplies:

power : /testbench/axi_dut/IVDD_0d81 ground : /testbench/axi_dut/VSS Power Switch: fpu_sw, File: /home/work/dpframe/upf/subsys.upf(64).

Output Supply port: vout_p(/testbench/axi_dut/IVDD_0d81)

Input Supply ports: 1. vin_p(/testbench/axi_dut/VDD_0d81) Control Ports:

1. ctrl_p(/testbench/axi_dut/pcu_inst/pd1_pwr_on) Switch States:

1. normal_working(ON) : (ctrl_p) 2. off_state(OFF) : (!ctrl_p)

Simulate

Questa PASim Native Simulation of RTL+UPF Just a switch on normal RTL or GLS simulation


HDL UPF Liberty

Optimize

Test Bench

n Compile as usual No change in source code

n Optimize with PA options Process UPF power intent Read Liberty libraries as needed Run static PA checks

n Simulate with PA options Generate reports/Testplan Visualize/debug power-managed

behavior

User PA Models

Compile


Questa Power Aware Verification Automatic checks and UPF/Power Aware Reports

Power Architecture Checks:

Isolation cells n Isolation cells are inserted

where required by power state definitions

n Isolation cells correctly handle dynamic signal behavior

Level shifters

n Level shifters are inserted where required by power state definitions

n Level shifters shift in correct direction

n Level shifters correctly handle dynamic signal behavior

Power Control Sequence Checks:

n Clock is disabled during power down n Isolation is enabled during power down

n Inputs do not toggle during power down n Retention/Isolation power is on and

stable during power down

n Retention registers are saved before power down

n Latch enable is correctly set when retention occurs

n Primary power is on and stable during power up

n Non-retention registers are reset at power up

n Power control signals do not glitch

25 Low Power Session - Verification Seminar


26

Evolution of Verification Process

Increasing number of features, hence increasing complexity of verification process

Verification done by design engineer

Verification done by teams of verification engineers

Verification done by a verification engineer

Verification by forcing all combinations of test vectors in a simulator

Verification by writing sophisticated test benches

Verification methodology which incorporates a complex suite of test benches


27

Major factors for bugs in chips

Percentage of designs going for re-spin

Reasons


28

Functional testing of a mobile phone

Phone calls Messages Games

Call

Message

Games

Call + Message

Call + Games

Message + Games

Call + Games+Message

0 10 20 30 40 50 60 70

Corner cases Functional Testing

Basic cases

X-Axis: % usage of a feature

% Y-Axis: features


29

Bug rate as the design matures

40186.0

40200.0

40214.0

40228.0

40242.0

40256.0

40270.0

40284.0

40298.0

40312.0

40326.0

40340.0

40354.0

40368.0

40382.0

40396.0

40410.0

0

20

40

60

80

100

120

140

160

180

B u g S ta tu s

Inc rem ents

C reated

Assigned

F ix ed

C losed

Moved

Total

D a te

S ta tu s`

Initially lots of Bugs are found in the design

As the design matures number of bugs detected will reduce

RTL Freeze point


30

Verification Gap

The big challenge confron/ng the industry


31

SV/UVM to the rescue

The big challenge confron/ng the industry

!

Verilog used to Verify designs

System Verilog and UVM used to reduce Verification gap


Cell-Aware Test in a Nutshell

32

n Traditional ATPG uses fault models that rely on fortuitous detection of cell-internal defects

n Cell-Aware ATPG improves detection by deterministically targeting defects internal to standard cells

n Defect type & location is derived from the layout of the cell

2. Extract

3. SPICE SIM

1. Layout

S0 S1 D0 D1 D2 Z

0 0 0 - 1 0

1 0 - 0 1 0

0 1 1 - 0 0

1 1 - 1 0 0 4. Model

5. ATPG

D0

D1

D2

S0

S1

Z


Hierarchical DFT Capabilities

n Ability to wrap/isolate individual cores/blocks

n Core level ATPG patterns reused at top level Patterns automatically retargeted to

top level and merged with other cores Patterns for duplicate cores only

generated once and retargeted to all instantiations

n Gray box generation for cores enables top level ATPG without need for complete gate level netlist

n Cores with DFT and test patterns completely reusable in any SoC

core 1a core 1b

core 2

33


34 34

Timing Closure: Need for CRPR

l Stands for Clk Reconvergence Pessimism Removal l If launching and capturing clocks share a common path,

the delay difference in common path due to usage of different derates will add additional pessimism to both setup and hold analysis.

l CRPR is used to remove this pessimism

D Q

FF2

D Q

FF1

1.67

1.77

1.85 A Y

A Y

A Y

Setup = 0.3

CK Q 1.5

B1

B2

B3

Numbers beside the gates show delays for the respective cell.

Common path

Timing derates: Launch path: 1.1 Capure path: 0.9


35 35

Timing Closure: Need for Path-Based Analysis

l Path-based analysis on the other hand, propagates slew belonging to the timing path under analysis

- For timing paths between A1 and A5, slew at pin A of A5 is used - For timing paths between A2 and A5, slew at pin B of A5 is used

A2 A

BZ

A4 A Z

A3 A

BZ

A5 A

B

ZA1 BZ


36 36

Timing Closure: Advanced OCV (AOCV)

l OCV applies a constant derate to the timing paths. l Timing Path spanning larger physical distance tends

to have larger systemic variations. Example: variation in gate length of transistors

l Timing Path with large logic depth (or large number of gates) have more number of gates which tend to cancel out variations resulting in reduced overall variation.

l AOCV reduces this pessimism by using the location and logic depth of each path analyzed


37 37

Need for Composite Current Source (CCS)

l Until 90nm process node, timing libraries used NLDM (Non-Linear Delay Modeling). l Some of the advantages of CCS (Composite Current

Source) delay model are - Accurate modeling of high impedance interconnect - Accurate slew calculation - Supports Temperature scaling - Supports timing calculation in designs using

multiple supply voltages

l CCS is the default timing library model used in 90nm and below process nodes


Continuously Increasing Physical Verification, Circuit Verification, and DFM Complexity

Dummy Fill Critical Area Critical Area

LVS

PEX

FinFET: PV, CV, DFM

2.5D / 3D-IC

Litho checks: IP

Single-dimension PV

LVS

Single-dimension PV

PEX

LVS

Single-dimension PV

Pattern Match

RDR /On-grid / On-pitch checks

Dummy / SmartFill

Litho checks: IP / full chip

ADP

LVS

Multi-dimension PV

Double Patterning (DP)

Delta-Voltage DRC/PERC checks

2.5D / 3D-IC

Pattern Match

RDR /On-grid / On-pitch checks

SmartFill (DP)

Litho checks: IP / full chip (DP)

ADP (DP)

LVS / Hyper Compare

Multi-dimension PV

Recommended Rule / CFA / MAS

Comprehensive Reliability checks

Recommended Rule / CFA / MAS

Spot Reliability checks

Req

uire

d R

ecom

men

ded

2002 130 nm

2006 90 nm

2008 65 nm

2010 40/28nm

2012 20/16/14 nm


Do I Have To? How Bad Could It Be?

Single Pattern Double Pattern


AMD TRM

n Performs: coloring, checking, & decomposition

n Why Calibre? Calibre MP is the golden in TSMC, ISDA

R&D, Samsung, etc Golden sign-off in combined nmDRC/MP

deck Faster debug with patented warning rings Calibre RealTime debug Calibre InRoute & Calibre AutoFix

Two Mask Layers w/Cuts & Error Rings

Original Drawn Layer

Two Mask Layers & Error Rings


Pattern Match with Calibre in 3 steps

Add pattern match checks to a Calibre SVRF

rule file

Specify layout path and type Specify output result database Input layer map ///*Pattern Matching Steps*/// Include pattern matching library Call pattern matching with associated input layers Output pattern matches to the results database Use pattern matches as input to another operation Output modified pattern matches to the result database

Execute pattern matching and view

results with Calibre RVE

Capture and export a pattern with a Calibre

layout viewer

1. 2. 3.


42

IR Drop distribution in a typical chip Wire-bond Package


43

Current Trend-- Flip-chip

Die

Solder bumps

Substrate BGA

Bumps attached to the die


44

Design Specs-- Present

Specifications: complex to very complex Operating Voltage : 600mv to 900mv

Transistor Feature Size: 15nm

Number of Transistors : Up-to 7 Billion say I/Os: A few hundred

Team Size: Sixty Engineers

Design Cycle Time: 6 to 8 months Post silicon Validation: DFT


45

We have come a long way

A Typical DSM Fab must meet Class 2 20 Generally has the capability of handling 12 wafers Costs about USD 6 Billion!!!


46

Summary

In this Field the only thing constant is change New tools, new flows, new products RTL design and Verification takes 60% of the total design time

and most of the job openings are in this area System Verilog and UVM expertise is in demand Low power design methodologies DFT, Implementation and timing analysis Physical design with PEX and DFM

Choose your projects wisely !! Know the differences between FPGA, ASIC and Full-custom design flows.


47

Thank You [email protected]

[email protected]

Documents

Advanced in the VLSI Design Flow.pdf