ADVANCED VLSI CHAP5-4

7/28/2019 ADVANCED VLSI CHAP5-4

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Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Topics

Sequential machine implementation:

clocking.

Sequential machine design.


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Sequential machine design

Two ways to specify sequential machine:

structure: interconnection of logic gates and

memory elements.

function: Boolean description of next-state and

output functions.

Best way depends on type of machine beingdescribed.


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Counter

Easy to specify as one-bit counter.

Harder to specify n-bit counter behavior.

Can specify n-bit counter as structure made

of 1-bit counters.


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One-bit counter

Truth table:

count Cin next Cout0 0 0 0

0 1 1 0

1 0 1 01 1 0 1


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One-bit counter operation

All operations are performed as s2.

XOR computes next value of this bit of

counter.

NAND/inverter compute carry-out.


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One-bit counter sticks

l1(latch) n(NAND) i(INV) x(XOR) l2(latch)

Cin

Cout

VDD

VSS

1

1

2

2


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n-bit counter structure


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State transition graphs/tables

Basic functional description of FSM.

Symbolic truth table for next-state, output

functions:

no structure of logic;

no encoding of states.

State transition graph and table are

functionally equivalent.


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01 string recognizer

Behavior of machine which recognizes 01

in continuous stream of bits:

time 0 1 2 3 4 5

input 0 0 1 1 0 1

state bit1 bit2 bit2 bit1 bit1 bit2next bit2 bit2 bit1 bit1 bit2 bit1

output 0 0 1 0 0 1


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01 recognizer operation

Waits for 0 to appear in statebit1.

Goes into separate statebit2 when 0

appears.

If 1 appears immediately after 0, cant have

a 01 on next cycle, so can go back to wait

for 0 in statebit1.


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State transition table

Symbolic state transition table:

input present next output

0 bit1 bit2 0

1 bit1 bit1 00 bit2 bit2 0

1 bit2 bit1 1


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State transition graph

Equivalent to state transition table:


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State assignment

Must find binary encoding for symbolic

statesstate assignment.

Choice of state assignment directly affectsboth the next-state and output logic:

area;

delay.

May also encode some machine

inputs/outputs.


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01 recognizer encoding

Choose bit1= 0, bit2 = 1:

input present next output

0 0 1 0

1 0 0 00 1 1 0

1 1 0 1


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Logic implementation

After encoding, truth table can be

implemented in gates:


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Traffic light controller

Intersection of two roads:

highway (busy);

farm (not busy).

Want to give green light to highway as

much as possible.

Want to give green to farm when needed.

Must always have at least one red light.


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Traffic light system

highway

farm road

sensor

traffic

light


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System operation

Sensor on farm road indicates when cars on

farm road are waiting for green light.

Must obey required lengths for green,yellow lights.


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Traffic light machine

Build controller out of two machines:

sequencer which sets colors of lights, etc.

timer which is used to control durations oflights.

Separate counter isolates logical design

from clock period. Separate counter greatly reduces number of

states in sequencer.


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Sequencer state transition graph

hwy-

green

farm-

green

hwy-

yellowfarm-

yellow

(cars & long) / 0 green red

cars & long / 1 green red

short /

0 yellow red

short / 1 yellow red



short /

0 red yellow

short/ 1 red yellow

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ADVANCED VLSI CHAP5-4