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Topics
State assignment.
Power optimization of sequential machines.
Design validation.
Sequential testing.
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State assignment
Encoding bits in symbolic state = state
assignment.
State assignment affects:
combinational logic area;
combinational logic delay;
memory element area.
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State assignment in n-space
0
s1 code = 111
s2 code = 110
1
1
1
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State assignment and delay
output
Next state
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Power optimization
Memory elements stop glitch propagation:
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Sequential testing
Much harder than combinational testing
cant set memory element values directly.
Must apply sequences to put machine in
proper state for test, be able to observe
value of test.
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Example
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Testing the machine
To test NAND for stuck-at-1, must set both
NAND inputs to 1.
Primary input i1 can be controlled directly.
To set lower NAND input, must set state to
ps0 = ps1 = 1.
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Example state machine
State codes:
s0 = 11
s1 = 10
s2 = 01
s3 = 00
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Controlling an FSM
Dont know initial state of machine.
Must find a sequence which drives machine
to required state independent of initial state.
State sequence for test:
* -> s0 -> s1 -> s3.
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Time-frame expansion
A model for sequential test: unroll machine
in time.
Time frame expansion illustrates how
single-stuck-at fault in sequential machine
appears to be multiple-SA fault.
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Time-frame expansion example
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Unreachable states
State assignment may cause some states to
be unreachable.
As a result, it may not be possible to apply
some required test values.
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Unreachable state example
s0 s1
s2
1/
0/
1/
0/0/ 1/
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Example
State codes:
s0 = 00
s1 = 01
s2 = 10.
This creates a fourth state which is
unreachable.
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Implemented FSM
00 01
10 11
1/ 0/
1/
0/0,1/0/
1/
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LSSD
LSSD = level-sensitive scan design.
Way to achieve full controllability,
observability of registers.
Links all registers in a scan chain.
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LSSD latch
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Partial scan
Full scan is expensivemust roll out and
roll in state many times during a set of tests.
Partial scan selects some registers forscanability.
Requires analysis to choose which registers
are best for scan.
