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DESIGN AND SIMULATION OF COMBINATIONALLOGIC CIRCUIT USING VHDL

Adder Multiplexer and Demultiplexer Encoder and Decoder Multiplier

ADDER

AIM :

To write a VHDL Code for Full Adder and Half Adder in Behavioral Modelling.

TOOLS REQUIRED:

XILINX ISE 9.1i

PROGRAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladder is

port(

a : in std_logic;

b : in std_logic;

cin : in std_logic;

sum : out std_logic;

carry : out std_logic

);

end fulladder;

architecture Behavioral of fulladder is

begin

sum <= (a xor b xor cin);

carry <= (a and b) or (b and cin) or (a and cin);

end Behavioral;

OUTPUT FOR FULL ADDER:

HALF ADDER:

PROGRAM:

library IEEE;




entity half is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end half;

architecture Behavioral of half is

begin

sum<=(a and (not b)) or ((not a) and b);

carry<= a and b;

end Behavioral;

OUTPUT FOR HALF ADDER:

MULTIPLEXER AND DEMULTIPLEXER

AIM :

To write a VHDL code for 4 : 1 Multiplexer and 1:4 Demultiplexer in

Behavioral Modelling

TOOLS REQUIRED:

XILINX ISE 9.1i

PROGRAM:

Multiplexer

library IEEE;




entity mux is

port(

inp : in std_logic_vector(3 downto 0);--mux input lines

sel : in std_logic_vector(1 downto 0);--mux sel input lines

muxout : out std_logic --mux output line

);

end mux;

architecture Behavioral of mux is

begin

process(inp,sel)

begin

case sel is

when "00" =>

muxout <= inp(0); -- mux O/P=1 I/P--

when "01" =>


when "10" =>

muxout <= inp(2); -- mux O/P=3 I/P—

when "11" =>


when others =>

end case;

end process;

end Behavioral;

OUTPUT MULTIPLEXER:

DEMULTIPLEXER:

PROGRAM:

library IEEE;




entity DEMUX5 is

Port ( dmuxin : in STD_LOGIC;

sel : in STD_LOGIC_VECTOR (1 downto 0);

oup : out STD_LOGIC_VECTOR (3 downto 0));

end DEMUX5;

architecture Behavioral of DEMUX5 is

begin

process(dmuxin,sel)

begin

case sel is

when"00"=>

oup(0)<=dmuxin;

oup(1)<='0';

oup(2)<='0';

oup(3)<='0';

when"01"=>

oup(0)<='0';

oup(1)<=dmuxin;

oup(2)<='0';

oup(3)<='0';

when"10"=>

oup(0)<='0';

oup(1)<='0';

oup(2)<=dmuxin;

oup(3)<='0';

when"11"=>

oup(0)<='0';

oup(1)<='0';

oup(2)<='0';

oup(3)<=dmuxin;

when others=>

end case;

end process;

end Behavioral;

OUTPUT FOR DEMULTIPLEXER:

ENCODER

AIM :

To write a VHDL Code for 8:3 Encoder and 3:8 Decoder in BehavioralModelling.

TOOLS REQUIRED:

XILINX ISE 9.1i

ENCODER

Program:

library IEEE;




entity encoder is

Port ( d : in STD_LOGIC_VECTOR (7 downto 0);

x : out STD_LOGIC;

y : out STD_LOGIC;

z : out STD_LOGIC);

end encoder;

architecture Behavioral of encoder is

begin

x<=d(4)or d(5)or d(6)or d(7);

y<=d(2)or d(3)or d(6)or d(7);

z<=d(1)or d(3)or d(5)or d(7);

end Behavioral;

OUTPUT FOR ENCODER:

DECODER:

PROGRAM:

library IEEE;




entity decoder is

Port ( s1 : in STD_LOGIC_VECTOR (1 downto 0);

e : in STD_LOGIC;

d0 : out STD_LOGIC;

d1 : out STD_LOGIC;

d2 : out STD_LOGIC;

d3 : out STD_LOGIC);

end decoder;

architecture Behavioral of decoder is

Port ( d : in STD_LOGIC_VECTOR (7 downto 0);

x : out STD_LOGIC;

y : out STD_LOGIC;

z : out STD_LOGIC);

end encod;

architecture Behavioral of encod is

begin

x<=d(4)or d(5)or d(6) or d(7);

y<=d(2) ord(3) or d(6) or d(7);

z<=d{1) or d(3) or d(5) or d(7):

end Behavioral;

OUTPUT FOR DECODER:

MULTIPLIER PROGRAM

Aim :

To write a VHDL code for 4 : 1 Multiplexer and 1:4 Demultiplexer inBehavioral Modelling

Tools Required:

XILINX ISE 9.1i

Program:

library IEEE;




entity m55 is

Port ( nibble1 : in STD_LOGIC_VECTOR (3 downto 0);

nibble2 : in STD_LOGIC_VECTOR (3 downto 0);

result : out STD_LOGIC_VECTOR (7 downto 0));

end entity m55;

architecture Behavioral of m55 is

begin

result<=nibble1*nibble2;

end architecture Behavioral;

MULTIPLIER OUTPUT

FLIP FLOPSAim :

To write a VHDL Code for 8:3 Encoder and 3:8 Decoder in BehavioralModelling.

Tools Required:

XILINX ISE 9.1i

Program:

library IEEE;




entity dflop is

Port ( x : in STD_LOGIC;

clk : in STD_LOGIC;

z : out STD_LOGIC);

end dflop;

architecture Behavioral of dflop is

component nand1

port(x,clk: in STD_LOGIC;

z: out STD_LOGIC);

end component;

component nand2

port(x,y: in STD_LOGIC;

z:out STD_LOGIC);

end component;

component notssss2

port(x,clk: in STD_LOGIC;

z:out STD_LOGIC);

end component;

begin

process(clk)

begin

if(clk='1' and clk'event)then

z<=not x;

end if;

end process;

end Behavioral;

OUTPUT FOR DFLIPFLOP

COUNTER

Aim : To write a VHDL code for 4 bit up/down counter in Behavioral Modelling.

Program:

library IEEE;




entity counter is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

enable : in STD_LOGIC;

updown : in STD_LOGIC;

count : inout STD_LOGIC_VECTOR (4 downto 0));

end counter;

architecture cntra of counter is

begin

process(clk)

begin

if(clk='1' and clk'event)then

if rst='1' then

count<="00000";

else

if(enable='1' and updown='1')then

count<=count+1;

else if enable='1' and updown='0' then

count<=count-1;

end if;

end if;

end if;

end if;

end process;

end cntra;

OUTPUT FOR UPDOWN COUNTER

SHIFT REGISTER

Aim : To write a VHDL code for 4 bit Serial in Parallel out shift register inBehavioral Modelling

Program:

library IEEE;




entity pase is

Port ( clk : in STD_LOGIC;

d1 : in STD_LOGIC;

load : in STD_LOGIC;

din : in STD_LOGIC_VECTOR (3 downto 0);

dout : out STD_LOGIC);

end pase;

architecture Behavioral of pase is

signal reg:std_logic_vector(3 downto 0);

begin

process(clk)

begin

if(clk='1' and clk' event)then

if load='1' then

reg<=din;

else

reg<=d1&reg(3 downto 1);

end if;

end if;

dout<=reg(0);

end process;

end Behavioral;

OUTPUT FOR SHIFT REGISTER :

FREQUENCY DIVIDER

Aim : To write a VHDL code for Frequency Divider in Behavioral Modelling

Program:

library IEEE;




entity freq is

Port ( din : inout STD_LOGIC;

q : inout STD_LOGIC;

clk : in STD_LOGIC;

reset : in STD_LOGIC);

end freq;

architecture Behavioral of freq is

begin

process(reset,clk)

begin

din<=not q;

if(reset='0')then

q<='0';

else if (clk'event and clk='1')then

q<=din;

end if;

end if;

end process;

end Behavioral;

OUTPUT:

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